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programmable controller for capacitance touch sensors ad7142 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features programmable capacitance-to-digital converter 36 ms update rate (@ maximum sequence length) better than 1 ff resolution 14 capacitance sensor input channels no external rc tuning components required automatic conversion sequencer on-chip automatic calibration logic automatic compensation for environmental changes automatic adaptive threshold and sensitivity levels on-chip ram to store calibration data spi?-compatible serial interface (ad7142) i 2 c?-compatible serial interface (ad7142-1) separate v drive level for serial interface interrupt output and gpio 32-lead, 5 mm x 5 mm lfcsp_vq 2.6 v to 3.6 v supply voltage low operating current full power mode: less than 1 ma low power mode: 50 a applications personal music and multimedia players cell phones digital still cameras smart hand-held devices television, a/v, and remote controls gaming consoles functional block diagram test v ref+ v ref? sdo/ sda sdi/ add0 sclk cs/ add1 int c shield src src v drive switch matrix 16-bit - cdc calibration engine control and data registers calibration ram 250khz excitation source serial interface and control logic interrupt and gpio logic power-on reset logic av cc agnd dgnd1 dgnd2 dv cc gpio 19 18 17 14 13 27 28 29 cin0 30 cin1 31 cin2 32 cin3 1 cin4 2 cin5 3 cin6 4 cin7 5 cin8 6 cin9 7 cin10 8 cin11 9 cin12 10 cin13 11 12 15 16 20 21 22 23 24 25 26 05702-001 figure 1. general description the ad7142 and ad7142-1 are integrated capacitance-to- digital converters (cdcs) with on-chip environmental calibration for use in systems requiring a novel user input method. the ad7142 and ad7142-1 can interface to external capacitance sensors implementing functions such as capacitive buttons, scroll bars, or wheels. the cdc has 14 inputs channeled through a switch matrix to a 16-bit, 250 khz sigma-delta (-) capacitance-to-digital converter. the cdc is capable of sensing changes in the capacitance of the external sensors and uses this information to register a sensor activation. the external sensors can be arranged as a series of buttons, as a scroll bar or wheel, or as a combination of sensor types. by programming the registers, the user has full control over the cdc setup. high resolution sensors require minor software to run on the host processor. the ad7142 and ad7142-1 have on-chip calibration logic to account for changes in the ambient environment. the calibration sequence is performed automatically and at continuous intervals, when the sensors are not touched. this ensures that there are no false or nonregistering touches on the external sensors due to a changing environment. the ad7142 has an spi-compatible serial interface, and the ad7142-1 has an i 2 c-compatible serial interface. both parts have an interrupt output, as well as a general-purpose input/ output (gpio). the ad7142 and ad7142-1 are available in a 32-lead, 5 mm 5 mm lfcsp_vq and operate from a 2.6 v to 3.6 v supply. the operating current consumption is less than 1 ma, falling to 50 a in low power mode (conversion interval of 400 ms).
ad7142 rev. a | page 2 of 72 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 3 specifications..................................................................................... 4 spi timing specifications (ad7142)......................................... 6 i 2 c timing specifications (ad7142-1) ..................................... 7 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 12 capacitance sensing theory..................................................... 12 operating modes........................................................................ 13 capacitance sensor input configuration.................................... 14 cin input multiplexer setup .................................................... 14 capacitance-to-digital converter................................................ 15 oversampling the cdc output ............................................... 15 capacitance sensor offset control.......................................... 15 conversion sequencer ............................................................... 15 cdc conversion sequence time ............................................ 16 cdc conversion results........................................................... 17 noncontact proximity detection ................................................. 18 recalibration ............................................................................... 18 proximity sensitivity .................................................................. 18 ff_skip_cnt............................................................................ 20 environmental calibration ........................................................... 22 capacitance sensor behavior without calibration............... 22 capacitance sensor behavior with calibration...................... 22 slow fifo ................................................................................ 23 slow_filter_update_lvl .............................................. 23 adaptive threshold and sensitivity ............................................. 24 interrupt output............................................................................. 26 cdc conversion complete interrupt..................................... 26 sensor touch interrupt.............................................................. 26 gpio int output control ....................................................... 28 outputs ............................................................................................ 30 excitation source........................................................................ 30 c shield output ............................................................................. 30 gpio ............................................................................................ 30 using the gpio to turn on/off an led................................... 30 serial interface ................................................................................ 31 spi interface ................................................................................ 31 i 2 c compatible interface........................................................... 33 v drive input ................................................................................. 35 pcb design guidelines ................................................................. 36 capacitive sensor board mechanical specifications ............. 36 chip scale packages ................................................................... 36 power-up sequence ....................................................................... 37 typical application circuits ......................................................... 38 register map ................................................................................... 39 detailed register descriptions ..................................................... 40 bank 1 registers ......................................................................... 40 bank 2 registers ......................................................................... 50 bank 3 registers ......................................................................... 57 outline dimensions ....................................................................... 69 ordering guide .......................................................................... 69
ad7142 rev. a | page 3 of 72 revision history 1/07rev. 0 to rev. a updated format.................................................................. universal changes to data sheet title .............................................................1 inserted figure 5................................................................................8 changes to figure 18 ......................................................................12 changes to operating modes section ..........................................13 changes to cin input multiplexer setup section ......................14 changes to table 9 and conversion sequencer section ............15 changes to noncontact proximity detection section ...............18 changes to recalibration section and table 12 ..........................18 deleted fifo control section.......................................................19 changes to figure 31 and table 13 ...............................................20 changes to figure 32 ......................................................................21 changes to capacitance sensor behavior with calibration section .....................................................................22 added slow fifo and slow_filter_update_lvl section ...................................23 changes to adaptive threshold and sensitivity section ...........24 inserted figure 37 and table 13 ....................................................25 deleted figure 42 ............................................................................29 changes to c shield output section ...............................................30 changes to figure 55 ......................................................................36 changes to power-up sequence section ......................................37 changes to figure 58 ......................................................................38 changes to table 21 ........................................................................42 changes to table 24 ........................................................................43 changes to table 25 ........................................................................44 changes to table 29 ........................................................................48 changes to table 31 ........................................................................49 6/06revision 0: initial version
ad7142 rev. a | page 4 of 72 specifications av cc , dv cc = 2.6 v to 3.6 v, t a = ?40 o c to +85c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments capacitance-to-digital converter update rate 35.45 36.86 38.4 ms 12 conversion stages in sequencer, decimation rate = 256 resolution 16 bit cin input range 1 2 pf no missing codes 16 bit guaranteed by design, but not production tested cin input leakage 25 na total unadjusted error 20 % output noise (peak-to-peak) 7 codes decimation rate = 128 3 codes decimation rate = 256 output noise (rms) 0.8 codes decimation rate = 128 0.5 codes decimation rate = 256 parasitic capacitance 40 pf parasitic capacitance to ground, per cin input guaranteed by characterization c bulk offset range 1 20 pf c bulk offset resolution 156.25 ff low power mode delay accuracy 4 % % of 200 ms, 400 ms, 600 ms, or 800 ms excitation source frequency 240 250 260 khz output voltage av cc v short-circuit source current 20 ma short-circuit sink current 50 ma maximum output load 250 pf capacitance load on source to ground c shield output drive 10 a c shield bias level av cc /2 v logic inputs (sdi, sclk, cs , sda, gpi test) v ih input high voltage 0.7 v drive v v il input low voltage 0.4 v i ih input high voltage ?1 a v in = v drive i il input low voltage 1 a v in = dgnd hysteresis 150 mv open-drain outputs (sclk, sda, int ) v ol output low voltage 0.4 v i sink = ?1 ma i oh output high leakage current 0.1 1 a v out = v drive logic outputs (sdo, gpo) v ol output low voltage 0.4 v i sink = 1 ma, v drive = 1.65 v to 3.6 v v oh output high voltage v drive ? 0.6 v i source = 1 ma, v drive = 1.65 v to 3.6 v sdo floating state leakage current 1 a pin three-state, leakage measured to gnd and dv cc gpo floating state leakage current ?5 2 a pin three-state, leakage measured to gnd and dv cc power av cc , dv cc 2.6 3.3 3.6 v v drive 1.65 3.6 v serial interface operating voltage i cc 0.9 1 ma in full power mode 20 a low power mode, converter idle, t a = 25c 16 33 a low power mode, converter idle 4.5 a full shutdown, t a = 25c 2.25 18 a full shutdown 1 c in and c bulk are defined in figure 2.
ad7142 rev. a | page 5 of 72 plastic overlay sensor board c bulk c in capacitive sensor 05702-054 figure 2. table 2. typical average current in low power mode, av cc , dv cc = 3.6 v, t= 25c, load of 50 pf on src pin, no load on src number of conversion stages (current values expressed in a) low power mode delay decimation rate 1 2 3 4 5 6 7 8 9 10 11 12 200 ms 128 26.4 33.3 40.1 46.9 53.5 60 66.5 72.8 79.1 85.2 91.3 97.3 256 35.6 49.1 62.2 74.9 87.3 99.3 111 122.3 133.4 144.2 154.7 164.9 400 ms 128 21.3 24.8 28.3 31.7 35.2 38.6 42 45.4 48.7 52 55.3 58.6 256 26 32.9 39.7 46.5 53.1 59.6 66.1 72.4 78.7 84.9 91 97 600 ms 128 19.6 21.9 24.3 26.6 28.9 31.2 33.5 35.8 38.1 40.4 42.6 44.8 256 22.7 27.4 32 36.6 41.1 45.6 50 54.4 58.8 63.1 67.4 71.6 800 ms 128 18.7 20.5 22.2 24 25.7 27.5 29.2 31 32.7 34.4 36.1 37.8 256 21.1 24.6 28.1 31.5 35 38.4 41.8 45.2 48.5 51.8 55.1 58.4 table 3. maximum average current in low power mode, av cc , dv cc = 3.6 v, load of 50 pf on src pin, no load on src number of conversion stages (current values expressed in a) low power mode delay decimation rate 1 2 3 4 5 6 7 8 9 10 11 12 200 ms 128 45.4 53.6 61.5 69.4 77.1 84.7 92.2 99.6 106.8 113.9 121 127.9 256 56.2 72 87.2 102 116.3 130.2 143.7 156.8 169.5 181.8 193.8 205.5 400 ms 128 39.5 43.6 47.7 51.8 55.8 59.8 63.7 67.6 71.5 75.4 79.2 83 256 45 53.1 61.1 68.9 76.7 84.3 91.8 99.1 106.4 113.6 120.6 127.5 600 ms 128 37.5 40.3 43 45.8 48.5 51.2 53.9 56.5 59.2 61.8 64.5 67.1 256 41.2 46.7 52.1 57.4 62.7 67.9 73.1 78.2 83.3 88.3 93.3 98.2 800 ms 128 36.5 38.6 40.7 42.7 44.8 46.8 48.8 50.9 52.9 54.9 56.9 58.9 256 39.3 43.4 47.5 51.5 55.6 59.5 63.5 67.4 71.3 75.2 79 82.8
ad7142 rev. a | page 6 of 72 spi timing specifications (ad7142) t a = ?40c to +85c; v drive = 1.65 v to 3.6 v; av cc , dv cc = 2.6 v to 3.6 v, unless otherwise noted. sample tested at 25c to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v cc ) and timed from a voltage level of 1.6 v. table 4. spi timing specifications parameter limit at t min , t max unit description f sclk 5 mhz max t 1 5 ns min cs falling edge to first sclk falling edge t 2 20 ns min sclk high pulse width t 3 20 ns min sclk low pulse width t 4 15 ns min sdi setup time t 5 15 ns min sdi hold time t 6 20 ns max sdo access time after sclk falling edge t 7 16 ns max cs rising edge to sdo high impedance t 8 15 ns min sclk rising edge to cs high cs scl k sdi sdo t 1 11 6 15 msb lsb 23 msb lsb 12 15 16 t 2 t 4 t 5 t 3 t 6 t 7 t 8 05702-002 figure 3. spi detailed timing diagram
ad7142 rev. a | page 7 of 72 i 2 c timing specifications (ad7142-1) t a = ?40c to +85c; v drive = 1.65 v to 3.6 v; av cc , dv cc = 2.6 v to 3.6 v, unless otherwise noted. sample tested at 25c to ensure compliance. all input signals timed from a voltage level of 1.6 v. table 5. i 2 c timing specifications 1 parameter limit unit description f sclk 400 khz max t 1 0.6 s min start condition hold time, t hd; sta t 2 1.3 s min clock low period, t low t 3 0.6 s min clock high period, t high t 4 100 ns min data setup time, t su; dat t 5 300 ns min data hold time, t hd; dat t 6 0.6 s min stop condition setup time, t su; sto t 7 0.6 s min start condition setup time, t su; sta t 8 1.3 s min bus free time between stop and start conditions, t buf t r 300 ns max clock/data rise time t f 300 ns max clock/data fall time 1 guaranteed by design, not production tested. 05702-003 sclk sdata t r t f t 2 t 5 t 1 t 3 t 4 stop start stop start t 7 t 6 t 1 t 8 figure 4. i 2 c detailed timing diagram
ad7142 rev. a | page 8 of 72 absolute maximum ratings table 6. parameter rating av cc to agnd, dv cc to dgnd ?0.3 v to +3.6 v analog input voltage to agnd ?0.3 v to av cc + 0.3 v digital input voltage to dgnd ?0.3 v to v drive + 0.3 v digital output voltage to dgnd ?0.3 v to v drive + 0.3 v input current to any pin except supplies 1 10 ma esd rating (human body model) 2.5 kv operating temperature range ?40c to +150c storage temperature range ?65c to +150c junction temperature 150c lfcsp_vq power dissipation 450 mw ja thermal impedance 135.7c/w ir reflow peak temperature 260c (0.5c) lead temperature (soldering 10 sec) 300c 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 200a i ol 200a i oh 1.6v to output pin c l 50pf 05702-004 figure 5. load circuit for digita l output timing specifications esd caution
ad7142 rev. a | page 9 of 72 pin configurations a nd function descriptions 0 5702-005 pin 1 indicator 1 cin3 2 cin4 3 cin5 4 cin6 5 cin7 6 cin8 7 cin9 8 cin10 24 cs 23 sclk 22 sdi 21 sdo 20 v drive 19 dgnd2 18 dgnd1 17 dv cc 9 c i n 1 1 1 0 c i n 1 2 1 1 c i n 1 3 1 2 c s h i e l d 1 3 a v c c 1 4 a g n d 1 5 s r c 1 6 s r c 3 2 c i n 2 3 1 c i n 1 3 0 c i n 0 2 9 v r e f ? 2 8 v r e f + 2 7 t e s t 2 6 g p i o 2 5 i n t top view ad7142 figure 6. ad7142 pin configuration pin 1 indicator 1 cin3 2 cin4 3 cin5 4 cin6 5 cin7 6 cin8 7 cin9 8 cin10 24 add1 23 sclk 22 add0 21 sda 20 v drive 19 dgnd2 18 dgnd1 17 dv cc 9 c i n 1 1 1 0 c i n 1 2 1 1 c i n 1 3 1 2 c s h i e l d 1 3 a v c c 1 4 a g n d 1 5 s r c 1 6 s r c 3 2 c i n 2 3 1 c i n 1 3 0 c i n 0 2 9 v r e f ? 2 8 v r e f + 2 7 t e s t 2 6 g p i o 2 5 i n t top view (not to scale) ad7142-1 05702-044 figure 7. ad7142-1 pin configuration table 7. pin function descriptions pin no. mnemonic description 1 cin3 capacitance sensor input. 2 cin4 capacitance sensor input. 3 cin5 capacitance sensor input. 4 cin6 capacitance sensor input. 5 cin7 capacitance sensor input. 6 cin8 capacitance sensor input. 7 cin9 capacitance sensor input. 8 cin10 capacitance sensor input. 9 cin11 capacitance sensor input. 10 cin12 capacitance sensor input. 11 cin13 capacitance sensor input. 12 c shield cdc shield potential output. requires 10 nf capacitor to ground. connect to external shield. 13 av cc cdc supply voltage. 14 agnd analog ground reference point for all cdc circuitry. tie to analog ground plane. 15 src cdc excitation source output. 16 src inverted excitation source output. 17 dv cc digital core supply voltage. 18 dgnd1 digital ground. 19 dgnd2 digital ground. 20 v drive serial interface operating voltage supply. 21 sdo (ad7142) spi serial data output. sda (ad7142-1) i 2 c serial data input/output. sda requires pull-up resistor. 22 sdi (ad7142) spi serial data input. add0 (ad7142-1) i 2 c address bit 0. 23 sclk clock input for serial interface. 24 cs (ad7142) spi chip select signal. add1 (ad7142-1) i 2 c address bit 1. 25 int general-purpose open-drain interrupt output. programmable polarity; requires pull-up resistor. 26 gpio programmable gpio. 27 test factory test pin. tie to ground. 28 v ref+ cdc positive reference input. normally tied to analog power. 29 v ref? cdc negative reference input. tie to analog ground. 30 cin0 capacitance sensor input. 31 cin1 capacitance sensor input. 32 cin2 capacitance sensor input.
ad7142 rev. a | page 10 of 72 typical performance characteristics 05702-053 i cc (a) v cc (v) 820 860 840 920 900 880 940 960 980 1000 2.7 2.92.8 3.0 3.1 3.2 3.3 3.4 3.5 3.6 device 3 device 1 device 2 figure 8. supply current vs. supply voltage (v cc = av cc + dv cc , i cc = ai cc + di cc ) 2.7 2.8 2.9 3.0 3.1 3.2 3.43.3 3.5 3.6 05702-051 i cc (a) v cc (v) 40 60 100 80 120 140 160 180 lp_conv_delay = 200ms lp_conv_delay = 400ms lp_conv_delay = 600ms lp_conv_delay = 800ms figure 9. low power supply current vs. supply voltage, decimation rate = 256 (v cc = av cc + dv cc , i cc = ai cc + di cc ) 2.7 2.8 2.9 3.0 3.10 3.2 3.43.3 3.5 3.6 05702-050 i cc (a) v cc (v) 20 40 60 80 100 120 lp_conv_delay = 200ms lp_conv_delay = 600ms lp_conv_delay = 800ms lp_conv_delay = 400ms figure 10. low power supply current vs. supply voltage decimation rate = 128 (v cc = av cc + dv cc , i cc = ai cc + di cc ) 1.40 1.55 1.70 1.85 2.00 2.15 2.30 2.45 2.7 2.9 2.8 3.0 3.1 3.2 3.3 3.4 3.5 3.6 shutdown i cc (a) v cc (v) 05702-052 device 2 device 3 device 1 figure 11. shutdown supply current vs. supply voltage (v cc = av cc + dv cc , i cc = ai cc + di cc ) 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0 50 100 150 200 250 300 350 400 450 500 05702-049 i cc (ma) capacitance load on source (pf) device 3 device 2 device 1 figure 12. supply current vs. capacitive load on src (i cc = ai cc + di cc ) 16015 16010 16005 16000 15995 15990 15985 15980 0 50 100 150 200 250 300 350 400 450 500 05702-048 cdc output code capacitance load on source (pf) device 3 device 2 device 1 figure 13. output code vs . capacitive load on src
ad7142 rev. a | page 11 of 72 960 780 800 820 840 860 880 900 920 940 ?40 120 100 3.6v 3.3v 2.7v 80604020 0 ?20 05702-056 supply current (a) temperature (c) figure 14. supply current vs. temperature (supply current = ai cc + di cc ) 12 10 8 6 4 2 0 ?40 120 100 80 6040 2.7v 3.3v 20 0 ?20 05702-057 supply current (a) temperature (c) 3.6v figure 15. shutdown suppl y current vs. temperature (supply current = ai cc + di cc ) 2.5 2.0 1.5 1.0 0.5 0 10 10m 100k 1k 05702-059 cdc peak-to-peak noise (codes) frequency (hz) 100mv 200mv 300mv 400mv 500mv figure 16. power supply sine wave rejection 180 160 140 120 100 80 60 40 20 0 100 10m 25mv 100mv 200mv 300mv 1m 10k 100k 1k 05702-060 cdc peak-to-peak noise (codes) square wave frequency (hz) 50mv figure 17. power supply square wave rejection
ad7142 rev. a | page 12 of 72 theory of operation the ad7142 and ad7142-1 are capacitance-to-digital converters (cdcs) with on-chip environmental compensation, intended for use in portable systems requiring high resolution user input. the internal circuitry consists of a 16-bit, - con- verter that converts a capacitive input signal into a digital value. there are 14 input pins on the ad7142 and ad7142-1, cin0 to cin13. a switch matrix routes the input signals to the cdc. the result of each capacitance-to-digital conversion is stored in on-chip registers. the host subsequently reads the results over the serial interface. the ad7142 contains an spi interface and the ad7142-1 has an i 2 c interface ensuring that the parts are compatible with a wide range of host processors. because the ad7142 and ad 7142-1 are identical parts, with the exception of the serial interface, ad7142 refers to both the ad7142 and ad7142-1 throughout this data sheet. the ad7142 interfaces with up to 14 external capacitance sensors. these sensors can be arranged as buttons, scroll bars, wheels, or as a combination of sensor types. the external sensors consist of electrodes on a single or multiple layer pcb that interfaces directly to the ad7142. the ad7142 can be set up to implement any set of input sensors by programming the on-chip registers. the registers can also be programmed to control features such as averaging, offsets, and gains for each of the external sensors. there is a sequencer on-chip to control how each of the capacitance inputs is polled. the ad7142 has on-chip digital logic and 528 words of ram that are used for environmental compensation. the effects of humidity, temperature, and other environmental factors can effect the operation of capacitance sensors. transparent to the user, the ad7142 performs continuous calibration to compen- sate for these effects, allowing the ad7142 to give error-free results at all times. the ad7142 requires some minor companion software that runs on the host or other microcontroller to implement high resolution sensor functions such as a scroll bar or wheel. however, no companion software is required to implement buttons, including 8-way button functionality. button sensors are implemented completely in digital logic on-chip. the ad7142 can be programmed to operate in either full power mode, or in low power automatic wake-up mode. the automatic wake-up mode is particularly suited for portable devices that require low power operation giving the user significant power savings coupled with full functionality. the ad7142 has an interrupt output, int , to indicate when new data has been placed into the registers. int is used to interrupt the host on sensor activation. the ad7142 operates from a 2.6 v to 3.6 v supply, and is available in a 32-lead, 5 mm 5 mm lfcsp_vq. capacitance sensing theory the ad7142 uses a method of sensing capacitance known as the shunt method. using this method, an excitation source is connected to a transmitter generating an electric field to a receiver. the field lines measured at the receiver are translated into the digital domain by a - converter. when a finger, or other grounded object, interferes with the electric field, some of the field lines are shunted to ground and do not reach the receiver (see figure 18 ). therefore, the total capacitance measured at the receiver decreases when an object comes close to the induced field. excitation signal 250khz - adc 16-bit data 05702-007 plastic cove r ad7142 tx rx pcb layer 1 figure 18. sensing capacitance method in practice, the excitation source and - adc are implemented on the ad7142, and the transmitter and receiver are constructed on a pcb that makes up the external sensor. registering a sensor activation when a sensor is approached, the total capacitance associated with that sensor, measured by the ad7142, changes. when the capacitance changes to such an extent that a set threshold is exceeded, the ad7142 registers this as a sensor touch. preprogrammed threshold levels are used to determine if a change in capacitance is due to a button being activated. if the capacitance exceeds one of the threshold limits, the ad7142 registers this as a true button activation. the same thresholds principle is used to determine if other types of sensors, such as sliders or scroll wheels, are activated.
ad7142 rev. a | page 13 of 72 complete solution for capacitance sensing analog devices, inc. provides a complete solution for capacitance sensing. the two main elements to the solution are the sensor pcb and the ad7142. if the application requires high resolution sensors, such as scroll bars or wheels, software is required that runs on the host processor. (no software is required for button sensors.) the memory requirements for the host depend on the sensor, and are typically 10 kb of code and 600 bytes of data memory. 05702-008 host processor 1 mips 10kb rom 600 bytes ram ad7142 spi or i 2 c sensor pcb figure 19. three part capacitance sensing solution analog devices supplies the sensor pcb footprint design libraries to the customer based on the customers specifications, and supplies any necessary software on an open-source basis. operating modes the ad7142 has three operating modes. full power mode, where the device is always fully powered, is suited for applications where power is not a concern (for example, game consoles that have an ac power supply). low power mode, where the part automatically powers down, is tailored to give significant power savings over full power mode, and is suited for mobile applications where power must be conserved. in shutdown mode, the part shuts down completely. the power_mode bits (bit 0 and bit 1) of the control register set the operating mode on the ad7142. the control register is at address 0x000. table 8 shows the power_mode settings for each operating mode. to put the ad7142 into shutdown mode, set the power_mode bits to either 01 or 11. table 8. power_mode settings power_mode bits operating mode 00 full power mode 01 full shutdown mode 10 low power mode 11 full shutdown mode the power-on default setting of the power_mode bits is 00, full power mode. full power mode in full power mode, all sections of the ad7142 remain fully powered at all times. when a sensor is being touched, the ad7142 processes the sensor data. if no sensor is touched, the ad7142 measures the ambient capacitance level and uses this data for the on-chip compensation routines. in full power mode, the ad7142 converts at a constant rate. see the cdc conversion sequence time section for more information. low power mode when in low power mode, the ad7142 power_mode bits are set to 10 upon device initialization. if the external sensors are not touched, the ad7142 reduces its conversion frequency, thereby greatly reducing its power consumption. the part remains in a reduced power state when the sensors are not touched. every lp_conv_delay ms (200, 400, 600 or 800 ms), the ad7142 performs a conversion and uses this data to update the compensation logic. when an external sensor is touched, the ad7142 begins a conversion se quence every 36 ms to read back data from the sensors. in low power mode, the total current consumption of the ad7142 is an average of the current used during a conversion, and the current used when the ad7142 is waiting for the next conversion to begin. for example, when lp_conv_delay l is 400 ms, the ad7142 typically uses 0.9 ma current for 36 ms, and 15 a for 400 ms of the conversion interval. note that these conversion timings can be altered through the register settings. see the cdc conversion sequence time section for more information. no yes yes no timeout 05702-009 any sensor touched? proximity timer count down conversion sequence every 36ms for sensor readback any sensor touched? conversion sequence every lp_conv_delay ms update compensation logic data path ad7142 setup and initialization power_mode = 10 figure 20. low power mode operation the time taken for the ad7142 to go from a full power state to a reduced power state, once the user stops touching the external sensors, is configurable. the pwr_dwn_timeout bits, in ambient compensation ctrl 0 register, at address 0x002, control the length of time the ad7142 takes before going into the reduced power state, once the sensors are not touched.
ad7142 rev. a | page 14 of 72 capacitance sensor input configuration each input connection from the external capacitance sensors to the ad7142 converter can be uniquely configured by using the registers in table 45 and tabl e 4 6 . these registers are used to configure input pin connection setups, sensor offsets, sensor sensitivities, and sensor limits for each stage. each sensor can be individually optimized. for example, a button sensor connected to stage0 can have different sensitivity and offset values than a button with a different function that is connected to a different stage. cin input multiplexer setup the cin_connection_setup registers in table 45 list the different options that are provided for connecting the sensor input pin to the cdc. the ad7142 has an on-chip multiplexer to route the input signals from each pin to the input of the converter. each input pin can be tied to either the negative or the positive input of the cdc, or it can be left floating. each input can also be internally connected to the c shield signal to help prevent cross coupling. if an input is not used, always connect it to c shield. connecting a cinx input pin to the positive cdc input results in a decrease in cdc output code when the corresponding sensor is activated. connecting a cinx input pin to the negative cdc input results in an increase in cdc output code when the corresponding sensor is activated. the multiplexer settings for each conversion sequence can be unique and different for each of the input pins, cin0 to cin13. for example, cin0 is connected to the negative cdc input for conversion stage1, left floating for sequencer stage1, and so on for all twelve conversion stages. two bits in each sequence stage register control the mux setting for the input pin. cin0 cin1 cin2 cin3 cin4 cin5 cin6 cin7 cin8 cin9 cin10 cin11 cin setting cin_connection _setup bits 00 cinx floating 01 cinx connected to negative cdc input 10 cinx connected to positive cdc input 11 cinx connected to c shield cdc ? + 05702-010 cin12 cin13 figure 21. input mux configuration options
ad7142 rev. a | page 15 of 72 capacitance-to-digital converter the capacitance-to-digital converter on the ad7142 has a - architecture with 16-bit resolution. there are 14 possible inputs to the cdc that are connected to the input of the converter through a switch matrix. the sampling frequency of the cdc is 250 khz. oversampling the cdc output the decimation rate, or oversampling ratio, is determined by bits[9:8] of the control register, as listed in table 9 . table 9. cdc decimation rate decimation bit value decimation rate cdc output rate per stage 00 256 3.072 ms 01 128 1.536 ms 10 1 C C 11 1 C C 1 do not use this setting. the decimation process on the ad7142 is an averaging process where a number of samples are taken and the averaged result is output. due to the architecture of the digital filter employed, the amount of samples taken (per stage) is equal to 3 times the decimation rate. so 3 256 or 3 128 samples are averaged to obtain each stage result. the decimation process reduces the amount of noise present in the final cdc result. however, the higher the decimation rate, the lower the output rate per stage, thus, a trade-off is possible between a noise-free signal and speed of sampling. capacitance sensor offset control there are two programmable dacs on board the ad7142 to null any capacitance sensor offsets. these offsets are associated with printed circuit board capacitance or capacitance due to any other source, such as connectors. in figure 22 , c in is the capacitance of the input sensors, and c bulk is the capacitance between layers of the sensor pcb. c bulk can be offset using the on-board dacs. plastic overlay sensor board c bulk c in capacitive sensor 05702-054 figure 22. capacitances around the sensor pcb a simplified block diagram in figure 23 shows how to apply the stage_offset registers to null the offsets. the 7-bit pos_afe_offset and neg_afe_offset registers program the offset dac to provide 0.16 pf resolution offset adjustment over a range of 20 pf. apply the positive and negative offsets to either the positive or the negative cdc input using the neg_afe_offset register and pos_afe_offset register. this process is only required once during the initial capacitance sensor characterization. 05702-011 pos_afe_offset 16-bit cdc neg_afe_offset +dac (20pf range) pos_afe_offset_swap bit neg_afe_offset_swap bit 7 7 16 cin src cin_connection_setup register senso r ?dac (20pf range) + _ figure 23. analog front-end o ffset control conversion sequencer the ad7142 has an on-chip sequencer to implement conversion control for the input channels. up to 12 conversion stages can be performed in one sequence. each of the 12 conversion stages can measure the input from a different sensor. by using the bank 2 registers, each stage can be uniquely configured to support multiple capacitance sensor interface requirements. for example, a slider sensor can be assigned to stage1 through stage8, with a button sensor assigned to stage0. the ad7142 on-chip sequence controller provides conversion control beginning with stage0. figure 24 shows a block diagram of the cdc conversion stages and cin inputs. a conversion sequence is defined as a sequence of cdc conversions starting at stage0 and ending at the stage determined by the value programmed in the sequence_stage_num register. depending on the number and type of capacitance sensors that are used, not all conversion stages are required. use the sequence_stage_num register to set the number of conversions in one sequence, depending on the sensor interface requirements. for example, this register would be set to 5 if the cin inputs were mapped to only six stages. in addition, set the stage_cal_en registers according to the number of stages that are used.
ad7142 rev. a | page 16 of 72 cin0 cin1 cin2 cin3 cin4 cin5 cin6 cin7 cin8 cin9 c in10 c in1 1 c in12 c in13 stage0 stage1 stage2 stage3 stage4 stage5 stage6 stage7 stage8 stage9 stage10 stage11 switch matrix - 16-bit adc c o nv e rs i o n s e q ue n c e 05702-012 figure 24. cdc conversion stages the number of required conversion stages depends completely on the number of sensors attached to the ad7142. figure 25 shows how many conversion stages are required for each sensor, and how many inputs each sensor requires to the ad7142. 05702-014 buttons stagex stagex 8-element slider cdc stagex + ? cdc stagex + ? cdc stagex + ? cdc stagex + ? cdc stagex + ? cdc stagex + ? cdc stagex + ? cdc stagex + ? ad7142 sequencer ad7142 sequencer s rc src s2 s3 s1 cdc + ? cdc + ? figure 25. sequencer setup for sensors a button sensor generally requires one sequencer stage; however, it is possible to configure two button sensors to operate differentially. only one button from the pair can be activated at a time; pressing both buttons together results in neither button being activated. this configuration requires one conversion stage, and is shown in figure 25 , b2 and b3. a scroll bar or slider sensor requires eight stages. the result from each stage is used by the host software to determine the users position on the scroll bar. the algorithm that performs this process is available from analog devices free of charge, on signing a software license. scroll wheels also require eight stages. the 8-way switch is made from two pairs of differential buttons. it, therefore, requires two conversion stages, one for each of the differential button pairs. it also requires a stage to measure whether the sensor is active. the buttons are orientated so that one pair makes up the top and bottom portions of the 8-way switch; the other pair makes up the left and right portions of the 8-way switch. cdc conversion sequence time the time required for one complete measurement for all 12 stages by the cdc is defined as the cdc conversion sequence time. the sequence_stage_num register and decimation register determine the conversion time as listed in table 1 0 . table 10. cdc conversion times for full power mode conversion time (ms) sequence_stage_num decimation = 128 decimation = 256 0 1.536 3.072 1 3.072 6.144 2 4.608 9.216 3 6.144 12.288 4 7.68 15.36 5 9.216 18.432 6 10.752 21.504 7 12.288 24.576 8 13.824 27.648 9 15.36 30.72 10 16.896 33.792 11 18.432 36.864 for example, operating with a decimation rate of 128, if the sequence_stage_num register is set to 5 for the conversion of six stages in a sequence, the conversion sequence time is 9.216 ms. full power mode cdc conversion sequence time the full power mode cdc conversion sequence time for all 12 stages is set by configuring the sequence_stage_num register, and decimation register as outlined in table 10 . figure 26 shows a simplified timing diagram of the full power cdc conversion time. the full power mode cdc conversion time, t conv_fp , is set using table 10 . notes 1. t conv_fp = value set from table 10. t conv_fp conversion sequence n conversion sequence n+1 conversion sequence n+2 cdc conversion 05702-015 figure 26. full power mode cdc conversion sequence time
ad7142 rev. a | page 17 of 72 low power mode cdc conversion sequence time with delay the frequency of each cdc conversion operating in the low power automatic wake-up mode is controlled by using the lp_conv_delay register located at address 0x000[3:2], in addition to the registers listed in table 10 . this feature provides some flexibility for optimizing the conversion time to meet system requirements vs. ad7142 power consumption. for example, maximum power savings is achieved when the lp_conv_delay register is set to 3. with a setting of 3, the ad7142 automatically wakes up, performing a conversion every 800 ms. table 11. lp_conv_delay settings lp_conv_delay bits delay between conversions 00 200 ms 01 400 ms 10 600 ms 11 800 ms figure 27 shows a simplified timing example of the low power cdc conversion time. as shown, the low power cdc conversion time is set by t conv_fp and the lp_conv_delay register. 05702-016 conversion sequence n cdc conversion conversion sequence n+1 lp_conv_delay t conv_fp t conv_lp figure 27. low power mode cdc conversion sequence time cdc conversion results certain high resolution sensors require the host to read back the cdc conversion results for processing. the registers required for host processing are located in the bank 3 registers. the host processes the data readback from these registers using a software algorithm, to determine position information. in addition to the results registers in the bank 3 registers, the ad7142 provides the 16-bit cdc output data directly, starting at address 0x00b of bank 1. reading back the cdc 16-bit conversion data register allows for customer-specific application data processing.
ad7142 rev. a | page 18 of 72 noncontact proximity detection the ad7142 internal signal processing continuously monitors all capacitance sensors for noncontact proximity detection. this feature provides the ability to detect when a user is approaching a sensor, at which time all internal calibration is immediately disabled and the ad7142 is automatically configured to detect a valid contact. the proximity control register bits are described in table 12 . the fp_proximity_cnt register bits and lp_proximity_cnt register bits control the length of the calibration disable period after the user leaves the sensor and proximity is no longer active, in full and low power modes. the calibration is disabled during this time and enabled again at the end of this period provided that the user is no longer approaching, or in contact with, the sensor. figure 28 and figure 29 show examples of how these registers are used to set the full and low power mode calibration disable periods. calibration disable period in full power mode = fp_proximity_cnt 16 time taken for one conversion sequence in full power mode calibration disable period in low power mode = lp_proximity_cnt 4 time taken for one conversion sequence in low power mode recalibration in certain situations, the proximity flag can be set for a long period, for example when a user hovers over a sensor for a long time. the environmental calibration on the ad7142 is suspended when proximity is detected, but changes may occur to the ambient capacitance level during the proximity event. this means the ambient value stored on the ad7142 no longer represents the actual ambient value. in this case, even when the user has left the sensor, the proximity flag may still be set. this situation could occur if the user interaction creates some moisture on the sensor causing the new sensor ambient value to be different from the expected value. in this situation, the ad7142 automatically forces a recalibration internally. this ensures that the ambient values are recalibrated regardless of how long the user hovers over a sensor. a recalibration ensures maximum ad7142 sensor performance. the ad7142 recalibrates automatically when the measured cdc value exceeds the stored ambient value by an amount determined by proximity_recal_lvl, for a set period of time known as the recalibration timeout. in full power mode, the recalibration timeout is controlled by fp_proximity_recal, and in low power mode, by lp_proximity_recal. recalibration timeout in full power mode = fp_proximity_recal time taken for one conversion sequence in full power mode recalibration timeout in low power mode = lp_proximity_recal time taken for one conversion sequence in low power mode figure 30 and figure 31 show examples of how the fp_proximity_recal and lp_proximity_recal register bits control the timeout period before a recalibration, operating in the full and low power modes. these figures show a user approaching a sensor followed by the user leaving the sensor and the proximity detection remains active after the user leaves the sensor. the measured cdc value exceeds the stored ambient value by the amount set in the proximity_recal_lvl bits, for the entire timeout period. the sensor is automatically recalibrated at the end of the timeout period. the forced recalibration takes two interrupt cycles, therefore, it should not be set again during this interval. proximity sensitivity the fast filter in figure 32 is used to detect when someone is close to the sensor (proximity). two conditions set the internal proximity detection signal using comparator 1 and comparator 2. comparator 1 detects when a user is approaching a sensor. the proximity_detection_rate register controls the sensitivity of comparator 1. for example, if proximity_detection_rate is set to 4, the proximity 1 signal is set when the absolute difference between word1 and word3 exceeds four lsb codes. comparator 2 detects when a user hovers over a sensor or approaches a sensor very slowly. the proximity_recal_lvl register (address 0x003) controls the sensitivity of comparator 2. for example, if proximity_recal_lvl is set to 75, the proximity 2 signal is set when the absolute difference between the fast filter average value and the ambient value exceeds 75 lsb codes. table 12. proximity control registers (see figure 32 ) register length register address description fp_proximity_cnt 4 bits 0x002 [7:4] calibr ation disable time in full power mode lp_proximity_cnt 4 bits 0x002 [11:8] calibr ation disable time in low power mode fp_proximity_recal 8 bits 0x004 [9:0] full power mode proximity recalibration time lp_proximity_recal 6 bits 0x004 [15:10] low power mode proximity recalibration time proximity_recal_lvl 8 bits 0x003 [13:8] proximity recalibration level proximity_detection_rate 6 bits 0x003 [7:0] proximity detection rate
ad7142 rev. a | page 19 of 72 proximity detection (internal) calibration (internal) 12345 678910111213141516 cdc conversion sequence (internal) 05702-017 calibration enabled calibration disabled t conv_fp user le a v es sensor area here user approaches sensor here t caldis figure 28. full power mode proximity detection example with fp_proximity_cnt = 1 05702-018 notes 1. sequence conversion time t conv_lp = t conv_fp + lp_conv_delay 2. proximity is set when user approaches the sensor at which time the internal calibration is disabled. 3. t caldis = ( t conv_lp lp_proximity_cnt 4) calibration enabled calibration disabled proximity detection (internal) calibration (internal) t caldis t conv_lp 12345678910111213141516 cdc conversion sequence (internal) user leaves sensor area here user approaches sensor here 1718 19 20 21 2223 24 figure 29. low power mode proximity detection with lp_proximity_cnt = 4 calibration enabled t recal_timeout 16 30 70 t conv_fp measured cdc value > stored ambient by proximity_recal _lvl recalibration time-out proximity detection (internal) calibration (internal) c dc conversion sequence (internal) recalibration counter (internal) 05702-019 notes 1. sequence conversion time t conv_fp determined from table 10 2. t caldis = t conv_fp fp_proximity_cnt 16 3. t recal_timeout = t conv_fp fp_proximity_recal 4. t recal = 2 t conv_fp user approaches sensor here user leaves sensor area here t caldis t recal calibration disabled figure 30. full power mode proximity detection with forced reca libration example with fp_proximity_cnt = 1 and fp_proximity_rec al = 40
ad7142 rev. a | page 20 of 72 05702-020 notes 1. sequence conversion time t conv_lp = t conv_fp + lp_conv_delay 2. t caldis = t conv_lp lp_proximity_cnt 4 3. t recal_timeout = t conv_fp lp_proximity_recal 4. t recal = 2 t conv_lp calibration enabled t recal_timeout 16 30 70 t conv_lp recalibration time-out proximity detection (internal) calibration (internal) c dc conversion sequence (internal) recalibration (internal) 05702-020 user approaches sensor here user leaves sensor area here measured cdc value > stored ambient by proximity_recal _lvl t recal t caldis calibration disabled figure 31. low power mode proximity detection with forced recalibration example with lp_proximity_cnt = 4 and lp_proximity_reca l = 40 ff_skip_cnt the proximity detection fast fifo is used by the on-chip logic to determine if proximity is detected. the fast fifo expects to receive samples from the converter at a set rate. ff_skip_cnt is used to normalize the frequency of the samples going into the fifo, re gardless of how many conversion stages are in a sequence. in register 0x02, bits[3:0] are the fast filter skip control, ff_skip_cnt. thi s value determines which cdc samples are not used (skipped) in the proximity detection fast fifo. determining the ff_skip_cnt value is required only once during the initial setup of the capacitance sensor interface. table 13 shows how ff_skip_cnt controls the update rate to the fast fifo. reco mmended value for this setting when using all 12 conversion stag es on the ad7142 is ff_skip_cnt = 0000 = no samples skipped. table 13. ff_skip_cnt settings fast fifo update rate ff_skip_cnt decimation = 128 decimation = 256 0 1.536 (sequence_stage_num + 1) ms 3.072 (sequence_stage_num + 1) ms 1 3.072 (sequence_stage_num + 1) ms 6.144 (sequence_stage_num + 1) ms 2 4.608 (sequence_stage_num + 1) ms 9.216 (sequence_stage_num + 1) ms 3 6.144 (sequence_stage_num + 1) ms 12.288 (sequence_stage_num + 1) ms 4 7.68 (sequence_stage_num + 1) ms 15.36 (sequence_stage_num + 1) ms 5 9.216 (sequence_stage_num + 1) ms 18.432 (sequence_stage_num + 1) ms 6 10.752 (sequence_stage_num + 1) ms 21.504 (sequence_stage_num + 1) ms 7 12.288 (sequence_stage_num + 1) ms 24.576 (sequence_stage_num + 1) ms 8 13.824 (sequence_stage_num + 1) ms 27.648 (sequence_stage_num + 1) ms 9 15.36 (sequence_stage_num + 1) ms 30.72 (sequence_stage_num + 1) ms 10 16.896 (sequence_stage_num + 1) ms 33.792 (sequence_stage_num + 1) ms 11 18.432 (sequence_stage_num + 1) ms 36.864 (sequence_stage_num + 1) ms 12 19.968 (sequence_stage_num + 1) ms 39.936 (sequence_stage_num + 1) ms 13 21.504 (sequence_stage_num + 1) ms 43.008 (sequence_stage_num + 1) ms 14 23.04 (sequence_stage_num + 1) ms 46.08 (sequence_stage_num + 1) ms 15 24.576 (sequence_stage_num + 1) ms 49.152 (sequence_stage_num + 1) ms
ad7142 rev. a | page 21 of 72 8 7 n = 0 proximity_detection_rate register 0x003 proximity_recal_lvl register 0x003 bank 3 registers proximity 2 slow_filter_update_lvl register 0x003 bank 3 registers sw1 16 notes 1. slow filter en is set and sw1 is closed when |stage_sf_ word 0?stage_sf_word 1 | exceeds the value programmed in the slow_filter_update_lvl register providing proximity is not set. 2. proximity 1 is set when |stage_ff_ word 0? stage_ff_word 3 | exceeds the value programmed in the proximity_detection_rate register. 3. proximity 2 is set when | average?ambient | exceeds the value programmed in the proximity_recal_lvl register. 4. description of comparator functions: comparator 1: used to detect when a user is approaching or leaving a sensor. comparator 2: used to detect when a user is hovering over a sensor, or approaching a sensor very slowly. fp_proximity_recal register 0x004 lp_proximity_recal register 0x004 proximity ambient value stage_sf_wordx cdc output code time sensor contact stage_sf_ambient bank 3 registers stage_ff_avg bank 3 registers fp_proximity_cnt register 0x002 lp_proximity_cnt register 0x002 proximity 1 proximity timing control logic word( n ) stage_sf_word7 stage_sf_word6 stage_sf_word5 stage_sf_word4 stage_sf_word3 stage_sf_word2 stage_sf_word1 stage_sf_word0 stage_ff_wordx also used to detect if the sensor ambient level has changed as a result of the user interaction. for example, humidity or dirt left behind on sensor. comparator 3: used to enable the slow filter update rate. the slow filter is updated when slow filter en is set and proximity is not set. word0 ? word3 cdc stage_ff_word0 stage_ff_word1 stage_ff_word2 stage_ff_word3 stage_ff_word4 stage_ff_word5 stage_ff_word6 stage_ff_word7 average ? ambient proximity comparator 1 comparator 2 comparator 2 slow_filter_en word0 ? word3 figure 32. ad7142 proximity detection and environmental calibration
ad7142 rev. a | page 22 of 72 environmental calibration the ad7142 provides on-chip capacitance sensor calibration to automatically adjust for environmental conditions that have an effect on the capacitance sensor ambient levels. capacitance sensor output levels are sensitive to temperature, humidity, and in some cases, dirt. the ad7142 achieves optimal and reliable sensor performance by continuously monitoring the cdc ambient levels and correcting for any changes by adjusting the stage_high_threshold and stage_low_ threshold register values, as described in equation 1 and equation 2. the cdc ambient level is defined as the capacitance sensor output level during periods when the user is not approaching or in contact with the sensor. the compensation logic runs automatically on every conversion after configuration when the ad7142 is not being touched. this allows the ad7142 to account for rapidly changing environ- mental conditions. the ambient compensation control registers give the host access to general setup and controls for the compensation algorithm. the ram stores the compensation data for each conversion stage, as well as setup information specific to each stage. figure 33 shows an example of an ideal capacitance sensor behavior where the cdc ambient level remains constant regardless of the environmental conditions. the cdc output shown is for a pair of differential button sensors, where one sensor caused an increase, and the other a decrease in measured capacitance when activated. the positive and negative sensor threshold levels are calculated as a percentage of the stage_offset_high and stage_offset_low values based on the threshold sensitivity settings and the ambient value. these values are sufficient to detect a sensor contact, resulting with the ad7142 asserting the int output when the threshold levels are exceeded. cdc output codes t stage_low_threshold stage_high_threshold cdc ambient value changing environmental conditions 05702-022 sensor 1 int asserted sensor 2 int asserted figure 33. ideal sensor behavior with a constant ambient level capacitance sensor behavior without calibration figure 34 shows the typical behavior of a capacitance sensor with no applied calibration. this figure shows ambient levels drifting over time as environmental conditions change. the ambient level drift has resulted in the detection of a missed user contact on sensor 2. this is a result of the initial low offset level remaining constant when the ambient levels drifted upward beyond the detection range. the capacitance sensor behavior with calibration section describes how the ad7142 adaptive calibration algorithm prevents errors such as this from occurring. cdc output codes t cdc ambient value drifting sensor 1 int asserted sensor 2 int not asserted changing environmental conditions stage_high_threshold stage_low_threshold 05702-023 figure 34. typical sensor behavior without calibration applied capacitance sensor behavior with calibration the ad7142 on-chip adaptive calibration algorithm prevents sensor detection errors such as the one shown in figure 34 . this is achieved by monitoring the cdc ambient levels and readjusting the initial stage_offset_high and stage_offset_low values according to the amount of ambient drift measured on each sensor. the internal stage_high_threshold and stage_low_threshold values described in equation 1 and equation 2 are automatically updated based on the new stage_offset_high and stage_offset_low values. this closed-loop routine ensures the reliability and repeatable operation of every sensor connected to the ad7142 under dynamic environmental conditions. figure 35 shows a simplified example of how the ad7142 applies the adaptive calibration process resulting in no interrupt errors under changing cdc ambient levels due to environmental conditions.
ad7142 rev. a | page 23 of 72 cdc output codes t sensor 1 int asserted 1 2 3 4 5 6 stage_high_threshold (post calibrated register value) 05702-024 changing environmental conditions notes 1. initial stage_offset_high register value 2. post calibrated register stage_high_threshold 3. post calibrated register stage_high_threshold 4. initial stage_low_threshold 5. post calibrated register stage_low_threshold 6. post calibrated register stage_low_threshold cdc ambient value drifting stage_low_threshold (post calibrated register value) sensor 2 int asserted figure 35. typical sensor behavior with calibration applied on the data path slow fifo as shown in figure 32 , there are a number of fifos implemented on the ad7142. these fifos are located in bank 3 of the on-chip memory. the slow fifos are used by the on-chip logic to monitor the ambient capacitance level from each sensor. avg_fp_skip and avg_lp_skip in register 0x001, bits[13:12] are the slow fifo skip control for full power mode, avg_fp_skip. bits[15:14] in the same register are the slow fifo skip control for low power mode, avg_lp_skip. these values determine which cdc samples are not used (skipped) in the slow fifo. changing theses values slows down or speeds up the rate at which the ambient capacitance value tracks the measured capacitance value read by the converter. slow fifo update rate in full power mode = avg_fp_skip [(3 decimation rate) (sequence_stage_num +1) (ff_skip_cnt +1) 4 10 -7 ] slow fifo update rate in low power mode = (avg_lp_skip +1) [(3 decimation rate) (sequence_stage_num +1) (ff_skip_cnt +1) 4 10 -7 ] / [(ff_skip_cnt +1 ) + lp_conv_delay] the slow fifo is used by the on-chip logic to track the ambient capacitance value. the slow fifo expects to receive samples from the converter at a rate of 33 ms to 40 ms. avg_fp_skip and avg_lp_skip are used to normalize the frequency of the samples going into the fifo, regardless of how many conversion stages are in a sequence. determining the avg_fp_skip and avg_lp_skip value is only required once during the initial setup of the capacitance sensor interface. recommended values for these settings when using all 12 conversion stages on the ad7142 are: avg_fp_skip = 00 = skip 3 samples avg_lp_skip = 00 = skip 0 samples slow_filter_update_lvl the slow_filter_update_lvl controls whether the most recent cdc measurement goes into the slow fifo (slow filter) or not. the slow filter is updated when the difference between the current cdc value and last value pushed into the slow fifo > slow_filter_update_lvl. this variable is in ambient control register 1, at address 0x003. y sensitivit threshold pos high offset stage high offset stage high offset stage ambient sf stage threshold high stage _ _ 16 4 _ _ _ _ 4 _ _ __ __ ? + + = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? equation 1. on-chip logic stage high threshold calculation y sensitivit threshold neg low offset stage low offset stage low offset stage ambient sf stage threshold low stage _ _ 16 4 _ _ _ _ 4 _ _ __ __ ? + + = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? equation 2. on-chip logic stage low threshold calculation
ad7142 rev. a | page 24 of 72 adaptive threshold and sensitivity the ad7142 provides an on-chip self-learning adaptive threshold and sensitivity algorithm. this algorithm continu- ously monitors the output levels of each sensor and automatically rescales the threshold levels proportionally to the sensor area covered by the user. as a result, the ad7142 maintains optimal threshold and sensitivity levels for all types of users regardless of their finger sizes. the threshold level is always referenced from the ambient level and is defined as the cdc converter output level that must be exceeded for a valid sensor contact. the sensitivity level is defined as how sensitive the sensor is before a valid contact is registered. figure 36 provides an example of how the adaptive threshold and sensitivity algorithm works. the positive and negative sensor threshold levels are calculated as a percentage of the stage_ offset_high and stage_offset_low values based on the threshold sensitivity settings and the ambient value. on configuration, initial estimates are supplied for both stage_offset_high and stage_offset_low after which the calibration engine automatically adjusts the stage_high_threshold and stage_low_ threshold values for sensor response. the ad7142 tracks the average maximum and minimum values measured from each sensor. these values give an indication of how the user is interacting with the sensor. a large finger gives a large average maximum or minimum value, and a small finger gives smaller values. when the average maximum or minimum value changes, the threshold levels are rescaled to ensure that the threshold levels are appropriate for the current user. figure 37 shows how the minimum and maximum sensor responses are tracked by the on-chip logic. reference a in figure 36 shows an undersensitive threshold level for a small finger user, demonstrating the disadvantages of a fixed threshold level. by enabling the adaptive threshold and sensitivity algorithm, the positive and negative threshold levels are determined by the pos_threshold_sensitivity and neg_threshold_ sensitivity register values and the most recent average maximum sensor output value. these registers can be used to select 16 different positive and negative sensitivity levels ranging between 25% and 95.32% of the most recent average maximum output level referenced from the ambient value. the smaller the sensitivity percentage setting, the easier it is to trigger a sensor activation. reference b shows that the positive adaptive threshold level is set at almost mid-sensitivity with a 62.51% threshold level by setting pos_threshold_ sensitivity = 1000. figure 36 also provides a similar example for the negative threshold level with neg_ threshold_sensitivity = 0001. . ambient level cdc output codes average max value stage_offset_high 25% 95.32% 62.51% = pos adaptive threshold level 25% 62.51% = pos adaptive threshold level 95.32% neg adaptive threshold level = 39.08% 25% 95.32% 25% 95.32% sensor contacted by small finger a v erage max v a lue stage_offset_low neg adaptive threshold level = 39.08% sensor contacted by large finger 05702-025 stage_offset_high is updated stage_offset_high is updated here stage_offset_low is updated here stage_offset_low is updated here a b figure 36. threshold sensitivity example with pos_threshol d_sensitivity = 1000 and neg_ threshold_sensitivity = 0011
ad7142 rev. a | page 25 of 72 - 16-bit cdc 16 stage_max_word0 stage_max_word1 stage_max_word2 stage_max_word3 stage_min_word0 stage_min_word1 stage_min_word2 stage_min_word3 stage_max_avg bank 3 registers stage_high_threshold bank 3 registers stage_max_temp bank 3 registers max level detection logic stage_min_avg bank 3 register3 stage_low_threshold bank 3 registers stage_min_temp bank 3 registers bank 3 registers bank 3 registers 05702-062 min level detection logic figure 37. tracking the minimum and maximum average sensor values table 13. additional information about environmen tal calibration and adaptive threshold registers register register location description neg_threshold_sensitivity bank 2 used in equation 2. this value is programmed once at start up. neg_peak_detect bank 2 used by internal adaptive threshold logic only. the neg_peak_detect is set to a percentage of the difference between the ambient cdc value, and the min average cdc value. if the output of the cdc gets within the neg_peak_detect percentage of the min averag e, only then is the min average value updated. pos_threshold_sensitivity bank 2 used in equation 1. this value is programmed once at start up. pos_peak_detect bank 2 used by internal adaptive threshold logic only. the pos_peak_detect is set to a percentage of the difference between the ambient cdc value, and the max average cdc value. if the output of the cdc gets within the pos_peak_detect percentage of the min average, only then is the max average value updated. stage_offset_low bank 2 used in equation 2. an initial value (based on sensor characterization) is programmed into this register at start up. the ad7142 on chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. set to 80% of the stage_offset_low_clamp value. stage_offset_high bank 2 used in equation 1. an initial value (based on sensor characterization) is programmed into this register at start up. the ad7142 on chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. set to 80% of the stage_offset_high_clamp value. stage_offset_high_clamp bank 2 used by internal environmental calibration and adaptive threshold algorithms only. an initial value (based on sensor characteriza tion) is programmed into this register at start up. the value in this register prevents a user from causing a sensors output value to exceed the expected nominal value. set to the maximum expected sensor respon se, maximum change in cdc output code . stage_offset_low_clamp bank 2 used by internal environmental calibration and adaptive threshold algorithms only. an initial value (based on sensor characteriza tion) is programmed into this register at start up. the value in this register prevents a user from causing a sensors output value to exceed the expected nominal value. set to the minimum expected sensor response, minimum change in cdc output code . stage_sf_ambient bank 3 used in equation 1 and equation 2. this is the ambient sensor output, when the sensor is not touched, as calcul ated using the slow fifo. stage_high_threshold bank 3 equation 1 value. stage_low_threshold bank 3 equation 2 value.
ad7142 rev. a | page 26 of 72 interrupt output the ad7142 has an interrupt output that triggers an interrupt service routine on the host processor. the int signal is on pin 25, and is an open-drain output. there are three types of interrupt events on the ad7142: a cdc conversion complete interrupt, a sensor threshold interrupt, and a gpio interrupt. each interrupt has enable and status registers. the conversion complete and sensor threshold interrupts can be enabled on a per conversion stage basis. the status registers indicate what type of interrupt triggered the int pin. status registers are cleared, and the int signal is reset high, during a read operation. the signal returns high as soon as the read address has been set up. cdc conversion complete interrupt the ad7142 interrupt signal asserts low to indicate the completion of a conversion stage, and new conversion result data is available in the registers. the interrupt can be independently enabled for each conversion stage. each conversion stage complete interrupt can be enabled via the stage_complete_en register (address 0x007). this register has a bit that corresponds to each conversion stage. setting this bit to 1 enables the interrupt for that stage. clearing this bit to 0 disables the conversion complete interrupt for that stage. in normal operation, the ad7142 interrupt is enabled only for the last stage in a conversion sequence. for example, if there are five conversion stages, the conversion complete interrupt for stage4 is enabled. int only asserts when all five conversion stages are complete, and the host can read new data from all five result registers. the interrupt is cleared by reading the stage_ complete_status_int register located at address 0x00a. register 0x00a is the conversion complete interrupt status register. each bit in this register corresponds to a conversion stage. if a bit is set, it means that the conversion complete interrupt for the corresponding stage was triggered. this register is cleared on a read, provided the underlying condition that triggered the interrupt has gone away. sensor touch interrupt use the sensor touch interrupt mode to interrupt the host processor only when the sensor is activated. configuring the ad7142 into this mode results in the interrupt being asserted when the user makes contact with the sensor and again when the user lifts off the sensor. the second interrupt is required to alert the host processor that the user is no longer contacting the sensor. the registers located at address 0x005 and address 0x006 are used to enable the interrupt output for each stage. the registers located at address 0x008 and address 0x009 are used to read back the interrupt status for each stage. figure 38 shows the interrupt output timing during contact with one of the sensors connected to stage0 when operating in the sensor touch interrupt mode. for a low limit configuration, the interrupt output is asserted as soon as the sensor is contacted and again after the user has stopped contacting the sensor. note: the interrupt output remains low until the host processor reads back the interrupt status registers located at address 0x008 and address 0x009. the interrupt output is asserted when there is a change in the threshold status bits. this could indicate that a user is now touching the sensor(s) for the first time, the number of sensors being touched has changed, or the user is no longer touching the sensor(s). reading the status bits in the interrupt status register shows the current sensor activations. 4 2 conversion stage serial readback notes: 1. user touching down on sensor 2. address 0x008 read b ack to clear interrupt 3. user lifting off of sensor 4. address 0x008 read b ack to clear interrupt stage0 stage1 int output 05702-055 figure 38. example of sensor touch interrupt
ad7142 rev. a | page 27 of 72 stage0 stage1 stage2 stage3 stage4 stage5 stage6 stage7 stage8 stage9 stage10 stage11 23 1 int conversions serial reads notes this is an example of a cdc conversion complete interrupt. this timing example shows that the interrupt output has been enabled to be asserted at the end of a conversion cycle for stage0, stage5, and stage9. the interrupts for all other stages have been disabled. stagex configuration programming notes for stage0, stage5, and stage9 (x = 0, 5, 9) stagex_low_int_en (address 0x005) = 0 stagex_high_int_en (address 0x006) = 0 stagex_complete_en (address 0x007) = 1 stagex configuration programming notes for stage1 through stage8, stage10, and stage11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 11) stagex_low_int_en (address 0x005) = 0 stagex_high_int_en (address 0x006) = 0 stagex_complete_en (address 0x007) = 0 serial readback requirements for stage0, stage5 and stage9. this readback operation is required to clear the interrupt output. 1. read the stage0_complete_status_int (address 0x00a) register 2. read the stage5_complete_status_int (address 0x00a) register 3. read the stage9_complete_status_int (address 0x00a) register 05702-026 figure 39. example of configuring the regist ers for end of conver sion interrupt setup 05702-027 42 1 int conversions serial reads notes this is an example of a sensor threshold interrupt for a case where the low threshold levels were exceeded. for example: the sensor connected to stage0 and stage9 were contacted and the low threshold levels were exceeded resulting in the interrupt being a sserted. the stage6 interrupt was not asserted because the user did not contact the sensor connected to stage6. stagex configuration programming notes for stage0, stage6, and stage9 (x = 0, 6, 9) stagex_low_int_en (address 0x005) = 1 stagex_high_int_en (address 0x006) = 0 stagex_complete_en (address 0x007) = 0 stagex configuration programming notes for stage1 through stage7, stage8, stage10, and stage11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 1 1) stagex_low_int_en (address 0x005) = 0 stagex_high_int_en (address 0x006) = 0 stagex_complete_en (address 0x007) = 0 serial readback requirements for stage0 and stage9. this readback operation is required to clear the interrupt output. 1. read the stage0_low_limit_int (address 0x008) register 2. read the stage5_low_limit_int (address 0x008) register stage0 stage1 stage2 stage3 stage4 stage5 stage6 stage7 stage8 stage9 stage10 stage11 figure 40. example of configuring the registers for sensor interrupt setup
ad7142 rev. a | page 28 of 72 gpio int output control the int output signal can be controlled by the gpio pin when the gpio is configured as an input. the gpio is configured as an input by setting the gpio_setup bits in the interrupt configuration register to 01. see the gpio section for more information on how to configure the gpio. enable the gpio interrupt by setting the gpio_int_en bit in register 0x007 to 1, or disable the gpio interrupt by clearing this bit to 0. the gpio status bit in the conversion complete interrupt status register reflects the status of the gpio interrupt. this bit is set to 1 when the gpio has triggered int . the bit is cleared on readback from the register, provided the condition that caused the interrupt has gone away. the gpio interrupt can be set to trigger on a rising edge, falling edge, high level, or low level at the gpio input pin. table 14 shows how the settings of the gpio_input_config bits in the interrupt enable register affect the behavior of int . figure 41 to figure 44 show how the interrupt output is cleared on a read from the cdc conversion complete interrupt status register. gpio input int output serial readback gpio input int output 1 notes 1. read gpio_status register to reset int output. gpio input high when register is read back gpio input low when register is read back 05702-028 figure 41. int output controlled by the gpio input example, gpio_setup = 01, gpio_input_config = 00 gpio input int output serial readback gpio input int output 1 gpio input high when register is read back gpio input low when register is read back notes 1. read gpio_status register to reset int output. 05702-029 figure 42. int output controlled by the gpio input example, gpio_setup = 01, gpio_input_config = 01
ad7142 rev. a | page 29 of 72 gpio input int output serial readback gpio input int output 1 gpio input low when register is read back gpio input high when register is read back notes 1. read gpio_status register to reset int output. 05702-030 figure 43. int output controlled by the gpio input example, gpio_setup = 01, gpio_input_config = 10 gpio input int output serial readback gpio input int output 1 gpio input low when register is read back gpio input high when register is read back notes 1. read gpio_status register to reset int output. 05702-031 figure 44. int output controlled by the gpio input example, gpio_setup = 01, gpio_input_config = 11 table 14. gpio interrupt behavior gpio_input_config gpio pin gpio_status int int behavior 00 = negative level triggered 1 0 1 not triggered 00 = negative level triggered 0 1 0 asserted when signal on gpio pin is low 01 = positive edge triggered 1 1 0 pulses low at low-to-high gpio transition 01 = positive edge triggered 0 0 1 not triggered 10 = negative edge triggered 1 0 1 pulses low at high-to-low gpio transition 10 = negative edge triggered 0 1 0 not triggered 11 = positive level triggered 1 1 0 asserted when signal on gpio pin is high 11 = positive level triggered 0 0 1 not triggered
ad7142 rev. a | page 30 of 72 outputs excitation source the excitation source onboard the ad7142 is a square wave source with a frequency of 250 khz. this excitation source forms the electric field between the transmitter and receiver in the external capacitance sensor pcb. the source is output from the ad7142 on two pins, the src pin and the src pin (outputs an inverted version of the source square wave). the src signal offsets large external sensor capacitances. src is not used in the majority of applications. the source output can be disabled from both output pins separately by writing to the control register bits (address 0x000[13:12]). setting bit 12 in this register to 1 disables the source output on the src pin. setting bit 13 in this register to 1 disables the inverted source output on the src pin. c shield output to prevent leakage from the external capacitance sensors, the sensor traces can be shielded. the ad7142 has a voltage output that can be used as the potential for any shield traces, c shield . the c shield voltage is equal to av dd /2. the c shield potential is derived from the output of the ad7142 internal amplifier, and is of equal potential to the cin input lines. because the shield is at the same potential as the sensor traces, no leakage to ground occurs. to eliminate any ringing on the c shield output, connect a 10 nf capacitor between the c shield pin and ground. this capacitor is required, whether c shield is used in the application or not . for most applications, c shield is not used, and a ground plane is used instead around the sensors. gpio the ad7142 has one gpio pin located at pin 26. it can be configured as an input or an output. the gpio_setup bits[13:12] in the interrupt enable register determine how the gpio pin is configured. table 15. gpio_setup bits gpio_setup gpio configuration 00 gpio disabled 01 input 10 output low 11 output high when the gpio is configured as an output, the voltage level on the pin is set to either a low level or a high level, as defined by the gpio_setup bits shown in table 15 . when the gpio is configured as an input, the gpio_input_config bits in the interrupt enable register determine the response of the ad7142 to a signal on the gpio pin. the gpio can be configured as either active high or active low, as well as either edge-triggered or level-triggered, as listed in table 16 . table 16. gpio_input_config bits gpio_input_config gpio configuration 00 triggered on negative level (active low) 01 triggered on positive edge (active high) 10 triggered on negative edge (active low) 11 triggered on positive level (active high) when gpio is configured as an input, it triggers the interrupt output on the ad7142. table 14 lists the interrupt output behavior for each of the gpio configuration setups. using the gpio to turn on/off an led the gpio on the ad7142 can be used to turn on and off leds by setting the gpio as either output high or low. setting the gpio output high turns on the led; setting the gpio output low turns off the led. the gpio pin connects to a transistor that provides the drive current for the led. suitable transistors include the ktc3875. ad7142 gpio v cc ktc3875 or similar 05702-061 figure 45. controlling leds using the gpio
ad7142 rev. a | page 31 of 72 serial interface the ad7142 is available with an spi serial interface. the ad7142-1 is available with an i 2 c-compatible interface. both parts are the same, with the exception of the serial interface. spi interface the ad7142 has a 4-wire serial peripheral interface (spi). the spi has a data input pin (sdi) for inputting data to the device, a data output pin (sdo) for reading data back from the device, and a data clock pin (sclk) for clocking data into and out of the device. a chip select pin ( cs ) enables or disables the serial interface. cs is required for correct operation of the spi interface. data is clocked out of the ad7142 on the negative edge of sclk, and data is clocked into the device on the positive edge of sclk. spi command word all data transactions on the spi bus begin with the master taking cs from high to low and sending out the command word. this indicates to the ad7142 whether the transaction is a read or a write, and gives the address of the register from which to begin the data transfer. the following bit map shows the spi command word. msb lsb 15 14 13 12 11 10 9:0 1 1 1 0 0 r/ w register address bits[15:11] of the command word must be set to 11100 to successfully begin a bus transaction. bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a write. bits[9:0] contain the target register address. when reading or writing to more than one register, this address indicates the address of the first register to be written to or read from. writing data data is written to the ad7142 in 16-bit words. the first word written to the device is the command word, with the read/write bit set to 0. the master then supplies the 16-bit input data-word on the sdi line. the ad7142 clocks the data into the register addressed in the command word. if there is more than one word of data to be clocked in, the ad7142 automatically incre- ments the address pointer, and clocks the next data-word into the next register. the ad7142 continues to clock in data on the sdi line until either the master finishes the write transition by pulling cs high, or the address pointer reaches its maximum value. the ad7142 address pointer does not wrap around. when it reaches its maximum value, any data provided by the master on the sdi line is ignored by the ad7142. notes 1. sdi bits are latched on sclk rising edges. sclk can idle high or low between write operations. 2. all 32 bits must be written: 16 bits for control word and 16 bits for data. 3. 16-bit command word settings for serial write operation: cw[15:11] = 11100 (enable word) cw[10] = 0 (r/w) cw[9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (10-bit msb justified register addr ess) cw 11 cw 10 cw 13 cw 12 sdi cw 15 cw 14 cw 9 cw 7 cw 6 cw 5 cw 4 cw 3 cw 2 cw 1 cw 0 d2 d1 d0 cw 8 t 1 t 4 16-bit command word 16-bit data 5 32 6 7 8 9 10 11 12 13 14 15 16 30 31 t 8 t 5 sclk 1234 d15 d14 d13 17 18 19 cs enable word r/w register address t 2 t 3 05702-033 figure 46. single register write spi timing
ad7142 rev. a | page 32 of 72 sdi cw 15 cw 14 cw 13 cw 8 cw 1 cw 0 d15 d14 sclk cw 12 notes 1. multiple sequential registers can be loaded continuously. 2. the first (lowest address) register addr ess is written, followed by multiple 16-bit data-words. 3. the addr ess automatically i ncrements with each 16-bit data-word (all 16 bits must be written). 4. cs is held low until the last desired register has been loaded. 5. 16-bit command word settings for sequential write operation: cw[15:11] = 11100 (enable word) cw[10] = 0 (r/w) cw[9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (starting msb justified register addr ess) d1 d0 d1 d0 d15 data for starting register address data for next register address d15 d14 1 32 234 15 16 17 18 31 34 33 48 47 49 cs cw 11 cw 10 cw 9 cw 7 cw 2 cw 6 cw 5 cw 4 cw 3 11 12 13 14 5678 910 16-bit command word enable word r/w starting register address 05702-034 figure 47. sequential register write spi timing notes 1. sdi bits are latched on sclk rising edges. sclk can idle high or low between write operations. 2. the 16-bit control word must be written on sdi: 5 bits for e nable word, 1 bit for r /w, and 10 bits for register address. 3. the register data is read back on the sdo pin. 4. x denotes don?t care. 5. xxx denotes high impedance three-state output. 6. cs is held low until all register bits have been read back. 7. 16-bit command word se ttings for single re adback operation: cw[15:11] = 11100 (enable word) cw[10] = 1 (r/w) cw[9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (10-bit msb justified register addr ess) cw 11 cw 10 cw 13 cw 12 sdi cw 15 cw 14 cw 9 cw 7 cw 6 cw 5 cw 4 cw 3 cw 2 cw 1 cw 0 xx x cw 8 t 1 t 4 16-bit readback d ata 5 32 6 7 8 9 10 11 12 13 14 15 16 30 31 t 8 t 5 s clk 1234 xxx 17 18 19 cs xxx xxx xxx xxx sdo xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx d2 d1 d0 xxx d15 d14 d13 t 6 t 7 xxx 16-bit command word enable word r/w register address t 2 t 3 05702-035 figure 48. single regist er readback spi timing reading data a read transaction begins when the master writes the command word to the ad7142 with the read/write bit set to 1. the master then supplies 16 clock pulses per data-word to be read, and the ad7142 clocks out data from the addressed register on the sdo line. the first data-word is clocked out on the first falling edge of sclk following the command word, as shown in figure 48 . the ad7142 continues to clock out data on the sdo line provided the master continues to supply the clock signal on sclk. the read transaction finishes when the master takes cs high. if the ad7142 address pointer reaches its maximum value, then the ad7142 repeatedly clocks out data from the addressed register. the address pointer does not wrap around.
ad7142 rev. a | page 33 of 72 05702-036 sdi cw 15 cw 14 cw 13 cw 8 cw 1 cw 0 xx sclk cw 12 xx xx x readback data for starting register address x x 1 32 2 3 4 15161718 31 34 33 4847 49 cs cw 11 cw 10 cw 9 cw 7 cw 2 cw 6 cw 5 cw 4 cw 3 11 12 13 14 5678 910 xxx xxx xxx xxx d15 d14 d1 d0 d1 d0 d15 d15 d14 xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx sdo 16-bit command word enable word r/w register address notes 1. multiple registers can be read back continuously. 2. the 16-bit control word must be written on sdi: 5 bits for enable word, 1 bit for r/w, and 10 bits for register address. 3. the address automatically increments with each 16-bit data-word being read back on the sdo pin. 4. cs is held low until all register bits have been read back. 5. x denotes don?t care. 6. xxx denotes high impedance three-state output. 7. 16-bit command word settings for sequential readback operation: cw[15:11] = 11100 (enable word) cw[10] = 1 (r/w) cw[9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (starting msb justified register address) readback data for next register address figure 49. sequential register read back spi timing i 2 c compatible interface the ad7142-1 supports the industry standard 2-wire i 2 c serial interface protocol. the two wires associated with the i 2 c timing are the sclk and the sda inputs. the sda is an i/o pin that allows both register write and register readback operations. the ad7142-1 is always a slave device on the i 2 c serial interface bus. it has a 7-bit device address, address 0101 1xx. the lower two bits are set by tying the add0 and add1 pins high or low. the ad7142-1 responds when the master device sends its device address over the bus. the ad7142-1 cannot initiate data transfers on the bus. table 17. ad7142-1 i 2 c device address add1 add0 i 2 c address 0 0 0101 100 0 1 0101 101 1 0 0101 110 1 1 0101 111 data transfer data is transferred over the i 2 c serial interface in 8-bit bytes. the master initiates a data transfer by establishing a start con- dition, defined as a high-to-low transition on the serial data line, sda, when the serial clock line, sclk, remains high. this indicates that an address/data stream follows. all slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (msb first) plus a r/ w bit that determines the direction of the data transfer. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as the acknowledge bit. all other devices on the bus now remain idle when the selected device waits for data to be read from, or written to it. if the r/ w bit is a 0, the master writes to the slave device. if the r/ w bit is a 1, the master reads from the slave device. data is sent over the serial bus in a sequence of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, since a low-to-high transition when the clock is high can be interpreted as a stop signal. the number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. when all data bytes are read or written, a stop condition is established. a stop condition is defined by a low-to-high transition on sda when sclk remains high. if the ad7142 encounters a stop condition, it returns to its idle condition, and the address pointer register resets to address 0x00.
ad7142 rev. a | page 34 of 72 notes 1. a start condition at the beginning is defined as a high-to-low trans ition on sda while sclk remains high. 2. a stop condition at the end is defined as a low-to-high transition on sda while sclk remains high. 3. 7-bit device address [dev a6:dev a0] = [0 1 0 1 1 x x], where x are don't care bits. 4. 16-bit register address[a15:a0] = [x, x, x, x, x, x, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0], where x are don?t care bits. 5. register address [a15:a8] and register address [a7:a0] are always separated by a low ack bit. 6. register data [d15:d8] and register data [d7:d0] are always separated by a low ack bit. sda dev a6 dev a5 dev a4 r/w a7 a6 sclk dev a3 a1 a0 1 26 234 17 18 19 20 25 dev a2 dev a1 dev a0 ack a15 a14 11 16 5678 910 start ad7142 device address a9 a8 register address[a15:a8] register address[a7:a0] ack d15 d14 d9 d8 35 27 28 29 34 37 36 43 38 44 d1 d0 d7 d6 register data[d15:d8 ] register data[d7:d0] ack ack 45 46 ack stop dev a6 dev a5 dev a4 123 start t 8 t 7 t 6 t 5 t 4 t 2 t 1 t 3 ad7142 device address 05702-037 figure 50. example of i 2 c timing for single register write operation writing data over the i 2 c bus the process for writing to the ad7142-1 over the i 2 c bus is shown in figure 50 and figure 52 . the device address is sent over the bus followed by the r/ w bit set to 0. this is followed by two bytes of data that contain the 10-bit address of the internal data register to be written. the following bit map shows the upper register address bytes. note that bit 7 to bit 2 in the upper address byte are dont care bits. the address is contained in the 10 lsbs of the register address bytes. msb lsb 7 6 5 4 3 2 1 0 x x x x x x register address bit 9 register address bit 8 the following bit map shows the lower register address bytes. msb lsb 7 6 5 4 3 2 1 0 reg. addr. reg. addr. reg. addr. reg. addr. reg. addr. reg. addr. reg. addr. reg. addr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the third data byte contains the 8 msbs of the data to be written to the internal register. the fourth data byte contains the 8 lsbs of data to be written to the internal register. the ad7142-1 address pointer register automatically increments after each write. this allows the master to sequentially write to all registers on the ad7142-1 in the same write transaction. however, the address pointer register does not wrap around after the last address. any data written to the ad7142-1 after the address pointer has reached its maximum value is discarded. all registers on the ad7142-1 are 16-bit. two consecutive 8-bit data bytes are combined and written to the 16-bit registers. to avoid errors, all writes to the device must contain an even number of data bytes. to finish the transaction, the master generates a stop condition on sdo, or generates a repeat start condition if the master is to maintain control of the bus. reading data over the i 2 c bus to read from the ad7142-1, the address pointer register must first be set to the address of the required internal register. the master performs a write transaction, and writes to the ad7142-1 to set the address pointer. the master then outputs a repeat start condition to keep control of the bus, or if this is not possible, ends the write transaction with a stop condition. a read transaction is initiated, with the r/ w bit set to 1. the ad7142-1 supplies the upper eight bits of data from the addressed register in the first readback byte, followed by the lower eight bits in the next byte. this is shown in figure 51 and figure 52 . because the address pointer automatically increases after each read, the ad7142-1 continues to output readback data until the master puts a no acknowledge and stop condition on the bus. if the address pointer reaches its maximum value, and the master continues to read from the part, the ad7142-1 repeatedly sends data from the last register addressed.
ad7142 rev. a | page 35 of 72 notes 1. a start condition at the beginning is defined as a high-to-low transition on sda while sclk remains high. 2. a stop condition at the end is defined as a low-to-high transition on sda while sclk remains high. 3. the master generates the ack at the end of the readback to signal that it does not want additional data. 4. 7-bit device addr ess [dev a6:dev a0] = [0 1 0 1 1 x x], where the two lsb x's are don't care bits. 5. 16-bit register addr ess[a15:a0] = [x, x, x, x, x, x, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0], where the upper lsb x?s are don?t care bits. 6. register addr ess [a15:a8] and register addr ess [a7:a0] are always sep arated by a low ack bits. 7. register data [d15:d8] and register data [d7:d0] are always separated by a low ack bit. 8. the r/w bit is set to a1 to indicate a readback operation. sda dev a6 dev a5 dev a4 r/w a7 a6 sclk dev a3 a1 a0 1 26 234 17 18 19 20 25 dev a2 dev a1 dev a0 ack a15 a14 11 16 5678 910 start ad7142-1 device address a9 a8 register address[a15:a8] register addr ess[a7:a0] ack 35 28 30 34 37 36 44 38 45 d1 d0 d7 d6 register data[d7:d0] sr ack 46 p dev a6 dev a5 dev a4 1 23 t 8 t 7 t 6 t 5 t 4 t 2 t 1 t 3 ad7142 device address ack 27 ad7142-1 device address dev a6 dev a5 dev a1 dev a0 05702-038 r/w 29 39 35 28 30 34 37 36 44 38 45 d1 d0 d7 d6 register data[d7:d0] s ack 46 p t 5 t 4 ad7142-1 device address dev a6 dev a5 dev a1 dev a0 r/w 29 39 p using repeated start separate read and write transactions ack ack figure 51. example of i 2 c timing for single regi ster readback operation ack write output from master output from ad7142 s p p ack 6-bit device address s = start bit p = stop bit sr = repeated start bit ack = acknowledge bit ack = no acknowledge bit register addr [15:8] register addr [7:0] write data high byte [15:8] write data low byte [7:0] write data high byte [15:8] write data low byte [7:0] ack read data high byte [15:8] read data low byte [7:0] ack w ack ack ack ack read (using repeated start) s ack 6-bit device address register addr high byte register addr low byte 6-bit device address read data high byte [15:8] ack w ack ack read data low byte [7:0] 05702-039 r sr p ack read data high byte [15:8] read data low byte [7:0] ack read (write transaction sets up register address) s ack 6-bit device address register addr high byte register addr low byte 6-bit device address read data high byte [15:8] ack w ack ack read data low byte [7:0] r p s ack ack figure 52. example of sequential i 2 c write and readback operation v drive input the supply voltage to all pins associated with both the i 2 c and spi serial interfaces (sdo, sdi, sclk, sda, and cs ) is separate from the main v cc supplies and is connected to the v drive pin. this allows the ad7142 to be connected directly to processors whose supply voltage is less than the minimum operating voltage of the ad7142 without the need for external level- shifters. the v drive pin can be connected to voltage supplies as low as 1.65 v and as high as dv cc .
ad7142 rev. a | page 36 of 72 pcb design guidelines capacitive sensor board me chanical specifications table 18. parameter symbol min typ max unit distance from edge of any sensor to edge of grounded metal object d 1 0.1 mm distance between sensor edges 1 d 2 = d 3 = d 4 0 mm distance between bottom of sensor board and controller board or grounded metal casing 2 d 5 1.0 mm 1 the distance is dependent on the application and the positioning of the switches relative to each other and with respect to th e users finger posi tioning and handling. adjacent sensors, with 0 minimum space betw een them, are impleme nted differentially. 2 the 1.0 mm specification is meant to preve nt direct sensor board contact with any cond uctive material. this specification does not guarantee no emi coupling from the controller board to the sensors. address potential emi coupling issues by placing a grounded metal shield between the capac itive sensor board and the main controller board as shown in figure 55. 05702-045 slider buttons capacitive sensor printed circuit d 1 d 3 d 4 8-way switch metal object d 2 figure 53. capacitive sensor board mechanicals top view d 5 controller printed circuit board or metal casing 0 5702-047 capacitive sensor board figure 54. capacitive sensor board mechanicals side view capacitive sensor board d 5 controller printed circuit board or metal casing grounded metal shield 05702-046 figure 55. capacitive sensor board with grounded shield chip scale packages the lands on the chip scale package (cp-32-3) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. center the land on the pad to maximize the solder joint size. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. to avoid shorting, provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the land pattern on the printed circuit board. thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. connect the printed circuit board thermal pad to gnd.
ad7142 rev. a | page 37 of 72 power-up sequence when the ad7142 is powered up, the following sequence is recommended when initially developing the ad7142 and p serial interface: 1. turn on the power supplies to the ad7142. 2. write to the bank 2 registers at address 0x080 through address 0x0df. these registers are contiguous so a sequential register write sequence can be applied. note: the bank 2 register values are unique for each application. register values are provided by analog devices after the sensor board has been developed. 3. write to the bank 1 registers at address 0x000 through address 0x007 as follows. these registers are contiguous so a sequential register write sequence can be applied (see figure 47 and figure 52 ). caution: at this time, address 0x001 must remain set to default value 0x0000 during this contiguous write operation. register values: address 0x000 = 0x00b2 address 0x001 = 0x0000 address 0x002 = 0x3230 address 0x003 = 0x14c8 address 0x004 = 0x0832 address 0x005 = 0x0000 address 0x006 = 0x0000 address 0x007 = 0x0001 (the ad7142 interrupt is asserted approximately every 36 ms.) 4. write to the bank 1 register, address 0x001 = 0x0fff. 5. read back the corresponding interrupt status register at address 0x008, address 0x009, or address 0x00a. this is determined by the interrupt output configuration as explained in the interrupt output section. note: the specific registers required to be read back depend on each application. analog devices provides this information after the sensor board has been developed. 6. repeat step 5 every time int is asserted. 05702-040 first conversion sequence conversion stage 0 conversion stages disabled 12345 678 91011012 910110 1 2 910110 1 second conversion sequence third conversion sequence figure 56. recommended start-up sequence
ad7142 rev. a | page 38 of 72 typical application circuits 05702-041 v drive 2.2k ? host with spi interface ss sck mosi miso int v host av cc, dv cc 1.8v av cc, dv cc 2.7v to 3.6v 0.1f 1f to 10f (optional) 24 23 22 21 20 19 18 17 9 10 12 11 13 14 15 16 10nf cin3 cin4 cin5 cin6 cin7 cin8 cin9 cin10 cin11 cin2 av cc src agnd cin12 cin13 c shield src cs int sdi sclk v drive dv cc dgnd1 sdo dgnd2 v ref+ test gpio cin0 cin1 v ref? ad7142 32 31 30 29 28 2 7 26 25 1 2 3 4 5 6 7 8 recom m ended to connect flooded plane around sensors to ground sensor pcb scroll wheel button button button button figure 57. typical application circuit with spi interface 2.2k ? sck sdo int cin3 cin4 cin5 cin6 cin7 cin8 cin9 cin10 cin2 cin11 av cc src agnd cin12 cin13 c shield src add1 int add0 sclk v drive dv cc dgnd1 sda dgnd2 v ref+ test gpio cin0 cin1 v ref? av cc, dv cc av cc, dv cc 2.7v to 3.6v 0.1f 1f to 10f (optional) ad7142-1 v drive v drive 2.2k ? 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 10nf host with i 2 c interface v drive 2.2k ? recommended to connect flooded plane around sensors to ground button button button slider 05702-042 figure 58. typical application circuit with i 2 c interface
ad7142 rev. a | page 39 of 72 register map the ad7142 address space is divided into three different register banks, referred to as bank 1, bank 2, and bank 3. figure 59 shows the division of these three banks. bank 1 contains control registers, cdc conversion control registers, interrupt enable registers, interrupt status registers, cdc 16-bit conversion data registers, device id registers, and proximity status registers. bank 2 contains the configuration registers used for uniquely configuring the cin inputs for each conversion stage. initialize the bank 2 configuration registers immediately after power-up to obtain valid cdc conversion result data. bank 3 registers contain the results of each conversion stage. these registers automatically update at the end of each conversion sequence. although these registers are primarily used by the ad7142 internal data processing, they are accessible by the host processor for additional external data processing, if desired. default values are undefined for bank 2 registers and bank 3 registers until after power-up and configuration of the bank 2 registers. 05702-043 register bank 1 addr 0x000 addr 0x018 addr 0x001 addr 0x005 addr 0x008 addr 0x00b addr 0x017 addr 0x7f0 set up control (1 register) calibration and set up (4 registers) interrupt enable (3 registers) interrupt status (3 registers) cdc 16-bit conversion data (12 registers) device id register invalid do not access 24 registers register bank 2 addr 0x080 addr 0x0b8 addr 0x088 addr 0x090 addr 0x098 addr 0x0a0 addr 0x0a8 addr 0x0b0 addr 0x0c8 addr 0x0c0 addr 0x0d8 addr 0x0d0 96 registers register bank 3 addr 0x0e0 addr 0x0b8 addr 0x088 addr 0x090 addr 0x098 addr 0x0a0 addr 0x0a8 addr 0x0b0 addr 0x0c8 addr 0x0c0 addr 0x28f addr 0x0d0 432 registers proximity status register addr 0x042 invalid do not access addr 0x043 stage11 configuration (8 registers) stage10 configuration (8 registers) stage9 configuration (8 registers) stage8 configuration (8 registers) stage7 configuration (8 registers) stage6 configuration (8 registers) stage5 configuration (8 registers) stage4 configuration (8 registers) stage3 configuration (8 registers) stage2 configuration (8 registers) stage1 configuration (8 registers) stage0 configuration (8 registers) stage0 results (36 registers) stage1 results (36 registers) stage2 results (36 registers) stage3 results (36 registers) stage4 results (36 registers) stage5 results (36 registers) stage6 results (36 registers) stage7 results (36 registers) stage8 results (36 registers) stage9 results (36 registers) stage10 results (36 registers) stage11 results (36 registers) figure 59. layout of bank 1 registers, bank 2 registers, and bank 3 registers
ad7142 rev. a | page 40 of 72 detailed register descriptions bank 1 registers all addresses and default values are expressed in hexadecimal. table 19. pwr_control register address data bit default value type name description 0x000 [1:0] 0 r/w power_mode operating modes 00 = full power mode (normal operation, cdc conversions approximately every 36 ms) 01 = full shutdown mode (no cdc conversions) 10 = low power mode (automatic wake up operation) 11 = full shutdown mode (no cdc conversions) [3:2] 0 lp_conv_delay low power mode conversion delay 00 = 200 ms 01 = 400 ms 10 = 600 ms 11 = 800 ms [7:4] 0 sequence_stage_num numb er of stages in sequence (n + 1) 0000 = 1 conversion stage in sequence 0001 = 2 conversion stages in sequence maximum value = 1011 = 12 conversion stages per sequence [9:8] 0 decimation adc decimation factor 00 = decimate by 256 01 = decimate by 128 10 = do not use this setting 11 = do not use this setting [10] 0 sw_reset software reset control (self-clearing) 1 = resets all registers to default values [11] 0 int_pol interrupt polarity control 0 = active low 1 = active high [12] 0 excitation_source excitation source control for pin 15 0 = enable output 1 = disable output [13] 0 src excitation source control for pin 16 0 = enable output 1 = disable output [15:14] 0 cdc_bias cdc bias current control 00 = normal operation 01 = normal operation + 20% 10 = normal operation + 35% 11 = normal operation + 50%
ad7142 rev. a | page 41 of 72 table 20. stage_cal_en register address data bit default value type name description 0x001 [0] 0 r/w stage0_cal_en stage0 calibration enable 0 = disable 1 = enable [1] 0 stage1_cal_en stage1 calibration enable 0 = disable 1 = enable [2] 0 stage2_cal_en stage2 calibration enable 0 = disable 1 = enable [3] 0 stage3_cal_en stage3 calibration enable 0 = disable 1 = enable [4] 0 stage4_cal_en stage4 calibration enable 0 = disable 1 = enable [5] 0 stage5_cal_en stage5 calibration enable 0 = disable 1 = enable [6] 0 stage6_cal_en stage6 calibration enable 0 = disable 1 = enable [7] 0 stage7_cal_en stage7 calibration enable 0 = disable 1 = enable [8] 0 stage8_cal_en stage8 calibration enable 0 = disable 1 = enable [9] 0 stage9_cal_en stage9 calibration enable 0 = disable 1 = enable [10] 0 stage10_cal_en stage10 calibration enable 0 = disable 1 = enable [11] 0 stage11_cal_en stage11 calibration enable 0 = disable 1 = enable [13:12] 0 avg_fp_skip full power mode skip control 00 = skip 3 samples 01 = skip 7 samples 10 = skip 15 samples 11 = skip 31 samples [15:14] 0 avg_lp_skip low power mode skip control 00 = use all samples 01 = skip 1 sample 10 = skip 2 samples 11 = skip 3 samples
ad7142 rev. a | page 42 of 72 table 21. amb_comp_ctrl0 register address data bit default value type name description 0x002 [3:0] 0 r/w ff_skip_cnt fast filter skip control (n+1) 0000 = no sequence of results are skipped 0001 = one sequence of results is skipped for every one allowed into fast fifo 0010 = two sequences of results are skipped for every one allowed into fast fifo 1011 = maximum value = 12 sequences of results are skipped for every one allowed into fast fifo [7:4] f fp_proximity_cnt calibration disable period in full power mode = fp_proximity_cnt 16 time taken for one conversion sequence in full power mode [11:8] f lp_proximity_cnt calibration disable period in low power mode = lp_proximity_cnt 4 time taken for one conversion sequence in low power mode [13:12] 0 pwr_down_timeout full power to low power mode timeout control 00 = 1.25 (fp_proximity_cnt) 01 = 1.50 (fp_proximity_cnt) 10 = 1.75 (fp_proximity_cnt) 11 = 2.00 (fp_proximity_cnt) [14] 0 forced_cal forced calibration control 0 = normal operation 1 = forces all conversion stages to recalibrate [15] 0 conv_reset conversion reset control (self-clearing) 0 = normal operation 1 = resets the conversion sequence back to stage0 table 22. amb_comp_ctrl1 register address data bit default value type name description 0x003 [7:0] 64 r/w proximity_recal_lvl proximity recalibration level [13:8] 1 proximity_detection_rate proximity detection rate [15:14] 0 slow_filter_update_lvl slow filter update level table 23. amb_comp_ctrl2 register address data bit default value type name description 0x004 [9:0] 3ff r/w fp_proximity_recal full power mode proximity recalibration time control [15:10] 3f lp_proximity_recal low power mode proximity recalibration time control
ad7142 rev. a | page 43 of 72 table 24. stage_low_int_en register address data bit default value type name description 0x005 [0] 0 r/w stage0_low_int_en stage0 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 low threshold is exceeded [1] 0 stage1_low_int_en stage1 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage1 low threshold is exceeded [2] 0 stage2_low_int_en stage2 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage2 low threshold is exceeded [3] 0 stage3_low_int_en stage3 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage3 low threshold is exceeded [4] 0 stage4_low_int_en stage4 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage4 low threshold is exceeded [5] 0 stage5_low_int_en stage5 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage5 low threshold is exceeded [6] 0 stage6_low_int_en stage6 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage6 low threshold is exceeded [7] 0 stage7_low_int_en stage7 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage7 low threshold is exceeded [8] 0 stage8_low_int_en stage8 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage8 low threshold is exceeded [9] 0 stage9_low_int_en stage9 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage9 low threshold is exceeded [10] 0 stage10_low_int_en stage10 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage10 low threshold is exceeded [11] 0 stage11_low_int_en stage11 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage11 low threshold is exceeded [13:12] 0 gpio_setup gpio setup 00 = disable gpio pin 01 = configure gpio as an input 10 = configure gpio as an active low output 11 = configure gpio as an active high output [15:14] 0 gpio_input_config gpio input configuration 00 = triggered on negative level 01 = triggered on positive edge 10 = triggered on negative edge 11 = triggered on positive level
ad7142 rev. a | page 44 of 72 table 25. stage_high_int_en register address data bit default value type name description 0x006 [0] 0 r/w stage0_high_int_en stage0 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 high threshold is exceeded [1] 0 stage1_high_int_en stage1 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage1 high threshold is exceeded [2] 0 stage2_high_int_en stage2 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage2 high threshold is exceeded [3] 0 stage3_high_int_en stage3 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage3 high threshold is exceeded [4] 0 stage4_high_int_en stage4 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage4 high threshold is exceeded [5] 0 stage5_high_int_en stage5 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage5 high threshold is exceeded [6] 0 stage6_high_int_en stage6 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage6 high threshold is exceeded [7] 0 stage7_high_int_en stage7 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage7 high threshold is exceeded [8] 0 stage8_high_int_en stage8 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage8 high threshold is exceeded [9] 0 stage9_high_int_en stage9 sensor high interrupt enable l 0 = interrupt source disabled 1 = int asserted if stage9 high threshold is exceeded [10] 0 stage10_high_int_en stage10 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage10 high threshold is exceeded [11] 0 stage11_high_int_en stage11 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage11 high threshold is exceeded [15:12] unused set unused register bits = 0
ad7142 rev. a | page 45 of 72 table 26. stage_complete_int_en register address data bit default value type name description 0x007 [0] 0 r/w stage0_complete_en stage0 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage0 conversion [1] 0 stage1_complete_en stage1 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage1 conversion [2] 0 stage2_complete_en stage2 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage2 conversion [3] 0 stage3_complete_en stage3 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage3 conversion [4] 0 stage4_complete_en stage4 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage4 conversion [5] 0 stage5_complete_en stage5 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage5 conversion [6] 0 stage6_complete_en stage6 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage6 conversion [7] 0 stage7_complete_en stage7 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage7 conversion [8] 0 stage8_complete_en stage8 conversion complete interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage8 conversion [9] 0 stage9_complete_en stage9 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage9 conversion [10] 0 stage10_complete_en stage10 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage10 conversion [11] 0 stage11_complete_en stage11 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage11 conversion [12] 0 gpio_int_en interrupt control when gpio input pin changes level 0 = disabled 1 = enabled [15:13] unused set unused register bits = 0
ad7142 rev. a | page 46 of 72 table 27. stage_low_limit_int register 1 address data bit default value type name description 0x008 [0] 0 r stage0_low_limit_int stage0 cdc conversion low limit interrupt result 1 = indicates stage0_low_threshold value was exceeded [1] 0 stage1_low_limit_int stage1 cdc conversion low limit interrupt result 1 = indicates stage1_low_threshold value was exceeded [2] 0 stage2_low_limit_int stage2 cdc conversion low limit interrupt result 1 = indicates stage2_low_threshold value was exceeded [3] 0 stage3_low_limit_int stage3 cdc conversion low limit interrupt result 1 = indicates stage3_low_threshold value was exceeded [4] 0 stage4_low_limit_int stage4 cdc conversion low limit interrupt result 1 = indicates stage4_low_threshold value was exceeded [5] 0 stage5_low_limit_int stage5 cdc conversion low limit interrupt result 1 = indicates stage5_low_threshold value was exceeded [6] 0 stage6_low_limit_int stage6 cdc conversion low limit interrupt result 1 = indicates stage6_low_threshold value was exceeded [7] 0 stage7_low_limit_int stage7 cdc conversion low limit interrupt result 1 = indicates stage7_low_threshold value was exceeded [8] 0 stage8_low_limit_int stage8 cdc conversion low limit interrupt result 1 = indicates stage8_low_threshold value was exceeded [9] 0 stage9_low_limit_int stage9 cdc conversion low limit interrupt result 1 = indicates stage9_low_threshold value was exceeded [10] 0 stage10_low_limit_int stage10 cdc conversion low limit interrupt result 1 = indicates stage10_low_threshold value was exceeded [11] 0 stage11_low_limit_int stage11 cdc conversion low limit interrupt result 1 = indicates stage11_low_threshold value was exceeded [15:12] unused set unused register bits = 0 1 registers self-clear to 0 af ter readback, provided that the limits are not exceeded.
ad7142 rev. a | page 47 of 72 table 28. stage_high_limit_int register 1 address data bit default value type name description 0x009 [0] 0 r stage0_high_limit_int stage0 cdc conversion high limit interrupt result 1 = indicates stage0_high_threshold value was exceeded [1] 0 stage1_high_limit_int stage1 cdc conversion high limit interrupt result 1 = indicates stage1_high_threshold value was exceeded [2] 0 stage2_high_limit_int stage2 cdc conversion high limit interrupt result 1 = indicates stage2_high_threshold value was exceeded [3] 0 stage3_high_limit_int stage3 cdc conversion high limit interrupt result 1 = indicates stage3_high_threshold value was exceeded [4] 0 stage4_high_limit_int stage4 cdc conversion high limit interrupt result 1 = indicates stage4_high_threshold value was exceeded [5] 0 stage5_high_limit_int stage5 cdc conversion high limit interrupt result 1 = indicates stage5_high_threshold value was exceeded [6] 0 stage6_high_limit_int stage6 cdc conversion high limit interrupt result 1 = indicates stage6_high_threshold value was exceeded [7] 0 stage7_high_limit_int stage7 cdc conversion high limit interrupt result 1 = indicates stage7_high_threshold value was exceeded [8] 0 stage8_high_limit_int stage8 cdc conversion high limit interrupt result 1 = indicates stage8_high_threshold value was exceeded [9] 0 stage9_high_limit_int stage9 cdc conversion high limit interrupt result 1 = indicates stage9_high_threshold value was exceeded [10] 0 stage10_high_limit_int stage10 cdc conversion high limit interrupt result 1 = indicates stage10_high_threshold value was exceeded [11] 0 stage11_high_limit_int stage11 cdc conversion high limit interrupt result 1 = indicates stage11_high_threshold value was exceeded [15:12] unused set unused register bits = 0 1 registers self-clear to 0 af ter readback, provided that the limits are not exceeded.
ad7142 rev. a | page 48 of 72 table 29. stage_complete_limit_int register 1 address data bit default value type name description 0x00a [0] 0 r stage0_complete_status_int stage0 conversion complete register interrupt status 1 = indicates stage0 conversion completed [1] 0 stage1_complete_status_int stage1 conversion complete register interrupt status 1 = indicates stage1 conversion completed [2] 0 stage2_complete_status_int stage2 conversion complete register interrupt status 1 = indicates stage2 conversion completed [3] 0 stage3_complete_status_int stage3 conversion complete register interrupt status 1 = indicates stage3 conversion completed [4] 0 stage4_complete_status_int stage4 conversion complete register interrupt status 1 = indicates stage4 conversion completed [5] 0 stage5_complete_status_int stage5 conversion complete register interrupt status 1 = indicates stage5 conversion completed [6] 0 stage6_complete_status_int stage6 conversion complete register interrupt status 1 = indicates stage6 conversion completed [7] 0 stage7_complete_status_int stage7 conversion complete register interrupt status 1 = indicates stage7 conversion completed [8] 0 stage8_complete_status_int stage8 conversion complete register interrupt status 1 = indicates stage8 conversion completed [9] 0 stage9_complete_status_int stage9 conversion complete register interrupt status 1 = indicates stage9 conversion completed [10] 0 stage10_complete_status_int stage10 conversion complete register interrupt status 1 = indicates stage10 conversion completed [11] 0 stage11_complete_status_int stage11 conversion complete register interrupt status 1 = indicates stage11 conversion completed [12] 0 gpio_status gpio input pin status 1 = indicates level on gpio pin has changed [15:13] unused set unused register bits = 0 1 registers self-clear to 0 af ter readback, provided that the limits are not exceeded. table 30. cdc 16-bit conversion data registers address data bit default value type name description 0x00b [15:0] 0 r adc_result_s0 stage0 cdc 16-bit conversion data 0x00c [15:0] 0 r adc_result_s1 stage1 cdc 16-bit conversion data 0x00d [15:0] 0 r adc_result_s2 stage2 cdc 16-bit conversion data 0x00e [15:0] 0 r adc_result_s3 stage3 cdc 16-bit conversion data 0x00f [15:0] 0 r adc_result_s4 stage4 cdc 16-bit conversion data 0x010 [15:0] 0 r adc_result_s5 stage5 cdc 16-bit conversion data 0x011 [15:0] 0 r adc_result_s6 stage6 cdc 16-bit conversion data 0x012 [15:0] 0 r adc_result_s7 stage7 cdc 16-bit conversion data 0x013 [15:0] 0 r adc_result_s8 stage8 cdc 16-bit conversion data 0x014 [15:0] 0 r adc_result_s9 stage9 cdc 16-bit conversion data 0x015 [15:0] 0 r adc_result_s10 stage10 cdc 16-bit conversion data 0x016 [15:0] 0 r adc_result_s11 stage11 cdc 16-bit conversion data
ad7142 rev. a | page 49 of 72 table 31. device id register address data bit default value type name description 0x017 [3:0] 2 r revision_code ad7142 revision code [15:4] e62 devid ad7142 device id = 1110 0110 0010 table 32. proximity status register address data bit default value type name description 0x042 [0] 0 r stage0_proximity_status stage0 proximity status register 1 = indicates proximity has been detected on stage0 [1] 0 r stage1_proximity_status stage1 proximity status register 1 = indicates proximity has been detected on stage1 [2] 0 r stage2_proximity_status stage2 proximity status register 1 = indicates proximity has been detected on stage2 [3] 0 r stage3_proximity_status stage3 proximity status register 1 = indicates proximity has been detected on stage3 [4] 0 r stage4_proximity_status stage4 proximity status register 1 = indicates proximity has been detected on stage4 [5] 0 r stage5_proximity_status stage5 proximity status register 1 = indicates proximity has been detected on stage5 [6] 0 r stage6_proximity_status stage6 proximity status register 1 = indicates proximity has been detected on stage6 [7] 0 r stage7_proximity_status stage7 proximity status register 1 = indicates proximity has been detected on stage7 [8] 0 r stage8_proximity_status stage8 proximity status register 1 = indicates proximity has been detected on stage8 [9] 0 r stage9_proximity_status stage9 proximity status register 1 = indicates proximity has been detected on stage9 [10] 0 r stage10_proximity_status stage10 proximity status register 1 = indicates proximity has been detected on stage10 [11] 0 r stage11_proximity_status stage11 proximity status register 1 = indicates proximity has been detected on stage11 [15:0] unused set unused register bits = 0
ad7142 rev. a | page 50 of 72 bank 2 registers all address values are expressed in hexadecimal. table 33. stage0 configuration registers address data bit default value type name description 0x080 [15:0] x r/w stage0_connection[6:0] stage0 cin(6:0) connection setup (see table 45 ) 0x081 [15:0] x r/w stage0_connection[13:7] stage0 cin(13:7) connection setup (see table 46 ) 0x082 [15:0] x r/w stage0_afe_offset stage0 afe offset control (see table 47 ) 0x083 [15:0] x r/w stage0_sensitivity stage0 sensitivity control (see table 48 ) 0x084 [15:0] x r/w stage0_offset_low stage0 initial offset low value 0x085 [15:0] x r/w stage0_offset_high stage0 initial offset high value 0x086 [15:0] x r/w stage0_offset_high_clamp stage0 offset high clamp value 0x087 [15:0] x r/w stage0_ offset_low_clamp stage0 offset low clamp value table 34. stage1 configuration registers address data bit default value type name description 0x088 [15:0] x r/w stage1_connection[6:0] stage1 cin(6:0) connection setup (see table 45 ) 0x089 [15:0] x r/w stage1_connection[13:7] stage1 cin(13:7) connection setup (see table 46 ) 0x08a [15:0] x r/w stage1_afe_offset stage1 afe offset control (see table 47 ) 0x08b [15:0] x r/w stage1_sensitivity stage1 sensitivity control (see table 48 ) 0x08c [15:0] x r/w stage1_offset_low stage1 initial offset low value 0x08d [15:0] x r/w stage1_offset_high stage1 initial offset high value 0x08e [15:0] x r/w stage1_offset_high_clamp stage1 offset high clamp value 0x08f [15:0] x r/w stage1_offset_low_clamp stage1 offset low clamp value table 35. stage2 configuration registers address data bit default value type name description 0x090 [15:0] x r/w stage2_connection[6:0] stage2 cin(6:0) connection setup (see table 45 ) 0x091 [15:0] x r/w stage2_connection[13:7] stage2 cin(13:7) connection setup (see table 46 ) 0x092 [15:0] x r/w stage2_afe_offset stage2 afe offset control (see table 47 ) 0x093 [15:0] x r/w stage2_sensitivity stage2 sensitivity control (see table 48 ) 0x094 [15:0] x r/w stage2_offset_low stage2 initial offset low value 0x095 [15:0] x r/w stage2_offset_high stage2 initial offset high value 0x096 [15:0] x r/w stage2_offset_high_clamp stage2 offset high clamp value 0x097 [15:0] x r/w stage2_offset_low_clamp stage2 offset low clamp value
ad7142 rev. a | page 51 of 72 table 36. stage3 configuration registers address data bit default value type name description 0x098 [15:0] x r/w stage3_connection[6:0] stage3 cin(6:0) connection setup (see table 45 ) 0x099 [15:0] x r/w stage3_connection[13:7] stage3 cin(13:7) connection setup (see table 46 ) 0x09a [15:0] x r/w stage3_afe_offset stage3 afe offset control (see table 47 ) 0x09b [15:0] x r/w stage3_sensitivity stage3 sensitivity control (see table 48 ) 0x09c [15:0] x r/w stage3_offset_low stage3 initial offset low value 0x09d [15:0] x r/w stage3_offset_high stage3 initial offset high value 0x09e [15:0] x r/w stage3_offset_high_clamp stage3 offset high clamp value 0x09f [15:0] x r/w stage3_offset_low_clamp stage3 offset low clamp value table 37. stage4 configuration registers address data bit default value type name description 0x0a0 [15:0] x r/w stage4_connection[6: 0] stage4 cin(6:0) connection setup (see table 45 ) 0x0a1 [15:0] x r/w stage4_connection[13: 7] stage4 cin(13:7) connection setup (see table 46 ) 0x0a2 [15:0] x r/w stage4_afe_offset stage4 afe offset control (see table 47 ) 0x0a3 [15:0] x r/w stage4_sensitivity stage4 sensitivity control (see table 48 ) 0x0a4 [15:0] x r/w stage4_offset_low stage4 initial offset low value 0x0a5 [15:0] x r/w stage4_offset_high stage4 initial offset high value 0x0a6 [15:0] x r/w stage4_offset_high_clamp stage4 offset high clamp value 0x0a7 [15:0] x r/w stage4_offset_low_clamp stage4 offset low clamp value table 38. stage5 configuration registers address data bit default value name type description 0x0a8 [15:0] x r/w stage5_connection[6: 0] stage5 cin(6:0) connection setup (see table 45 ) 0x0a9 [15:0] x r/w stage5_connection[13: 7] stage5 cin(13:7) connection setup (see table 46 ) 0x0aa [15:0] x r/w stage5_afe_offset stage5 afe offset control (see table 47 ) 0x0ab [15:0] x r/w stage5_sensitivity stage5 sensitivity control (see table 48 ) 0x0ac [15:0] x r/w stage5_offset_low stage5 initial offset low value 0x0ad [15:0] x r/w stage5_offset_high stage5 initial offset high value 0x0ae [15:0] x r/w stage5_offset_high_clamp stage5 offset high clamp value 0x0af [15:0] x r/w stage5_offset_low_clamp stage5 offset low clamp value
ad7142 rev. a | page 52 of 72 table 39. stage6 configuration registers address data bit default value type name description 0x0b0 [15:0] x r/w stage6_connection[6: 0] stage6 cin(6:0) connection setup (see table 45 ) 0x0b1 [15:0] x r/w stage6_connection[13: 7] stage6 cin(13:7) connection setup (see table 46 ) 0x0b2 [15:0] x r/w stage6_afe_offset stage6 afe offset control (see table 47 ) 0x0b3 [15:0] x r/w stage6_sensitivity stage6 sensitivity control (see table 48 ) 0x0b4 [15:0] x r/w stage6_offset_low stage6 initial offset low value 0x0b5 [15:0] x r/w stage6_offset_high stage6 initial offset high value 0x0b6 [15:0] x r/w stage6_offset_high_clamp stage6 offset high clamp value 0x0b7 [15:0] x r/w stage6_offset_low_clamp stage6 offset low clamp value table 40. stage7 configuration registers address data bit default value type name description 0x0b8 [15:0] x r/w stage7_connection[6: 0] stage7 cin(6:0) connection setup (see table 45 ) 0x0b9 [15:0] x r/w stage7_connection[13: 7] stage7 cin(13:7) connection setup (see table 46 ) 0x0ba [15:0] x r/w stage7_afe_offset stage7 afe offset control (see table 47 ) 0x0bb [15:0] x r/w stage7_sensitivity stage7 sensitivity control (see table 48 ) 0x0bc [15:0] x r/w stage7_offset_low stage7 initial offset low value 0x0bd [15:0] x r/w stage7_offset_high stage7 initial offset high value 0x0be [15:0] x r/w stage7_offset_high_clamp stage7 offset high clamp value 0x0bf [15:0] x r/w stage7_offset_low_clamp stage7 offset low clamp value table 41. stage8 configuration registers address data bit default value type name description 0x0c0 [15:0] x r/w stage8_connection[6: 0] stage8 cin(6:0) connection setup (see table 45 ) 0x0c1 [15:0] x r/w stage8_connection[13: 7] stage8 cin(13:7) connection setup (see table 46 ) 0x0c2 [15:0] x r/w stage8_afe_offset stage8 afe offset control (see table 47 ) 0x0c3 [15:0] x r/w stage8_sensitivity stage8 sensitivity control (see table 48 ) 0x0c4 [15:0] x r/w stage8_offset_low stage8 initial offset low value 0x0c5 [15:0] x r/w stage8_offset_high stage8 initial offset high value 0x0c6 [15:0] x r/w stage8_offset_high_clamp stage8 offset high clamp value 0x0c7 [15:0] x r/w stage8_offset_low_clamp stage8 offset low clamp value
ad7142 rev. a | page 53 of 72 table 42. stage9 configuration registers address data bit default value type name description 0x0c8 [15:0] x r/w stage9_connection[6: 0] stage9 cin(6:0) connection setup (see table 45 ) 0x0c9 [15:0] x r/w stage9_connection[13: 7] stage9 cin(13:7) connection setup (see table 46 ) 0x0ca [15:0] x r/w stage9_afe_offset stage9 afe offset control (see table 47 ) 0x0cb [15:0] x r/w stage9_sensitivity stage9 sensitivity control (see table 48 ) 0x0cc [15:0] x r/w stage9_offset_low stage9 initial offset low value 0x0cd [15:0] x r/w stage9_offset_high stage9 initial offset high value 0x0ce [15:0] x r/w stage9_offset_high_clamp stage9 offset high clamp value 0x0cf [15:0] x r/w stage9_offset_low_clamp stage9 offset low clamp value table 43. stage10 configuration registers address data bit default value type name description 0x0d0 [15:0] x r/w stage10_connection[6 :0] stage10 cin(6:0) connection setup (see table 45 ) 0x0d1 [15:0] x r/w stage10_connection[13: 7] stage10 cin(13:7) connection setup (see table 46 ) 0x0d2 [15:0] x r/w stage10_afe_offset stage10 afe offset control (see table 47 ) 0x0d3 [15:0] x r/w stage10_sensitivity stage10 sensitivity control (see table 48 ) 0x0d4 [15:0] x r/w stage10_offset_low stage10 initial offset low value 0x0d5 [15:0] x r/w stage10_offset_high stage10 initial offset high value 0x0d6 [15:0] x r/w stage10_offset_high_clamp stage10 offset high clamp value 0x0d7 [15:0] x r/w stage10_offset_low_clamp stage10 offset low clamp value table 44. stage11 configuration registers address data bit default value type name description 0x0d8 [15:0] x r/w stage11_connection[6 :0] stage11 cin(6:0) connection setup (see table 45 ) 0x0d9 [15:0] x r/w stage11_connection[13: 7] stage11 cin(13:7) connection setup (see table 46 ) 0x0da [15:0] x r/w stage11_afe_offset stage11 afe offset control (see table 47 ) 0x0db [15:0] x r/w stage11_sensitivity stage11 sensitivity control (see table 48 ) 0x0dc [15:0] x r/w stage11_offset_low stage11 initial offset low value 0x0dd [15:0] x r/w stage11_offset_high stage11 initial offset high value 0x0de [15:0] x r/w stage11_offset_high_clamp stage11 offset high clamp value 0x0df [15:0] x r/w stage11_offset_low_clamp stage11 offset low clamp value
ad7142 rev. a | page 54 of 72 table 45. stagex detailed cin (0:6) conn ection setup description (x = 0 to 11) data bit default value type name description [1:0] x r/w cin0_connection_setup cin0 connection setup 00 = cin0 not connected to cdc inputs 01 = cin0 connected to cdc negative input 10 = cin0 connected to cdc positive input 11 = cin0 connected to bias (connect unused cin inputs) [3:2] x r/w cin1_connection_setup cin1 connection setup 00 = cin1 not connected to cdc inputs 01 = cin1 connected to cdc negative input 10 = cin1 connected to cdc positive input 11 = cin1 connected to bias (connect unused cin inputs) [5:4] x r/w cin2_connection_setup cin2 connection setup 00 = cin2 not connected to cdc inputs 01 = cin2 connected to cdc negative input 10 = cin2 connected to cdc positive input 11 = cin2 connected to bias (connect unused cin inputs) [7:6] x r/w cin3_connection_setup cin3 connection setup 00 = cin3 not connected to cdc inputs 01 = cin3 connected to cdc negative input 10 = cin3 connected to cdc positive input 11 = cin3 connected to bias (connect unused cin inputs) [9:8] x r/w cin4_connection_setup cin4 connection setup 00 = cin4 not connected to cdc inputs 01 = cin4 connected to cdc negative input 10 = cin4 connected to cdc positive input 11 = cin4 connected to bias (connect unused cin inputs) [11:10] x r/w cin5_connection_setup cin5 connection setup 00 = cin5 not connected to cdc inputs 01 = cin5 connected to cdc negative input 10 = cin5 connected to cdc positive input 11 = cin5 connected to bias (connect unused cin inputs) [13:12] x r/w cin6_connection_setup cin6 connection setup 00 = cin6 not connected to cdc inputs 01 = cin6 connected to cdc negative input 10 = cin6 connected to cdc positive input 11 = cin6 connected to bias (connect unused cin inputs) [15:14] x unused set unused register bits = 0
ad7142 rev. a | page 55 of 72 table 46. stagex detailed cin (7:13) conn ection setup description (x = 0 to 11) data bit default value type name description [1:0] x r/w cin7_connection_setup cin7 connection setup 00 = cin7 not connected to cdc inputs 01 = cin7 connected to cdc negative input 10 = cin7 connected to cdc positive input 11 = cin7 connected to bias (connect unused cin inputs) [3:2] x r/w cin8_connection_setup cin8 connection setup 00 = cin8 not connected to cdc inputs 01 = cin8 connected to cdc negative input 10 = cin8 connected to cdc positive input 11 = cin8 connected to bias (connect unused cin inputs) [5:4] x r/w cin9_connection_setup cin9 connection setup 00 = cin9 not connected to cdc inputs 01 = cin9 connected to cdc negative input 10 = cin9 connected to cdc positive input 11 = cin9 connected to bias (connect unused cin inputs) [7:6] x r/w cin10_connection_setup cin10 connection setup 00 = cin10 not connected to cdc inputs 01 = cin10 connected to cdc negative input 10 = cin10 connected to cdc positive input 11 = cin10 connected to bias (connect unused cin inputs) [9:8] x r/w cin11_connection_setup cin11 connection setup 00 = cin11 not connected to cdc inputs 01 = cin11 connected to cdc negative input 10 = cin11 connected to cdc positive input 11 = cin11 connected to bias (connect unused cin inputs) [11:10] x r/w cin12_connection_setup cin12 connection setup 00 = cin12 not connected to cdc inputs 01 = cin12 connected to cdc negative input 10 = cin12 connected to cdc positive input 11 = cin12 connected to bias (connect unused cin inputs) [13:12] x r/w cin13_connection_setup cin13 connection setup 00 = cin13 not connected to cdc inputs 01 = cin13 connected to cdc negative input 10 = cin13 connected to cdc positive input 11 = cin13 connected to bias (connect unused cin inputs) [14] x neg_afe_offset_disable negative afe offset enable control 0 = enable 1 = disable [15] x pos_afe_offset_disable positive afe offset enable control 0 = enable 1 = disable
ad7142 rev. a | page 56 of 72 table 47. stagex detailed offset control description (x = 0 to 11) data bit default value type name description [6:0] x r/w neg_afe_offset negative afe offset setting (20 pf range) 1 lsb value = 0.16 pf of offset [7] x r/w neg_afe_offset_swap negative afe offset swap control 0 = neg_afe_offset applied to cdc negative input 1 = neg_afe_offset applied to cdc positive input [14:8] x r/w pos_afe_offset positive afe offset setting (20 pf range) 1 lsb value = 0.16 pf of offset [15] x r/w pos_afe_offset_swap positive afe offset swap control 0 = pos_afe_offset applied to cdc positive input 1 = pos_afe_offset applied to cdc negative input table 48. stagex detailed sensitivity control description (x = 0 to 11) data bit default value type name description [3:0] x r/w neg_threshold_sensitivity negative threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [6:4] x r/w neg_peak_detect ne gative peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [7] x r/w unused set unused register bits = 0 [11:8] x r/w pos_threshold_sensitivity positive threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [14:12] x r/w pos_peak_detect positive peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [15] x r/w unused set unused register bits = 0
ad7142 rev. a | page 57 of 72 bank 3 registers all address values are expressed in hexadecimal. table 49. stage0 results registers address data bit default value type name description 0x0e0 [15:0] x r/w stage0_conv_data stage0 cdc 16-bit conversion data (copy of data in stage0_conv_data register) 0x0e1 [15:0] x r/w stage0_ff_word0 stage0 fast fifo word0 0x0e2 [15:0] x r/w stage0_ff_word1 stage0 fast fifo word1 0x0e3 [15:0] x r/w stage0_ff_word2 stage0 fast fifo word2 0x0e4 [15:0] x r/w stage0_ff_word3 stage0 fast fifo word3 0x0e5 [15:0] x r/w stage0_ff_word4 stage0 fast fifo word4 0x0e6 [15:0] x r/w stage0_ff_word5 stage0 fast fifo word5 0x0e7 [15:0] x r/w stage0_ff_word6 stage0 fast fifo word6 0x0e8 [15:0] x r/w stage0_ff_word7 stage0 fast fifo word7 0x0e9 [15:0] x r/w stage0_sf_word0 stage0 slow fifo word0 0x0ea [15:0] x r/w stage0_sf_word1 stage0 slow fifo word1 0x0eb [15:0] x r/w stage0_sf_word2 stage0 slow fifo word2 0x0ec [15:0] x r/w stage0_sf_word3 stage0 slow fifo word3 0x0ed [15:0] x r/w stage0_sf_word4 stage0 slow fifo word4 0x0ee [15:0] x r/w stage0_sf_word5 stage0 slow fifo word5 0x0ef [15:0] x r/w stage0_sf_word6 stage0 slow fifo word6 0x0f0 [15:0] x r/w stage0_sf_word7 stage0 slow fifo word7 0x0f1 [15:0] x r/w stage0_sf_ambient stage0 slow fifo ambient value 0x0f2 [15:0] x r/w stage0_ff_avg stage0 fast fifo average value 0x0f3 [15:0] x r/w stage0_peak_detect_ word0 stage0 peak fifo word0 value 0x0f4 [15:0] x r/w stage0_peak_detect_ word1 stage0 peak fifo word1 value 0x0f5 [15:0] x r/w stage0_max_word0 stage0 maximum value fifo word0 0x0f6 [15:0] x r/w stage0_max_word1 stage0 maximum value fifo word1 0x0f7 [15:0] x r/w stage0_max_word2 stage0 maximum value fifo word2 0x0f8 [15:0] x r/w stage0_max_word3 stage0 maximum value fifo word3 0x0f9 [15:0] x r/w stage0_max_avg stage0 average maximum fifo value 0x0fa [15:0] x r/w stage0_high_threshold stage0 high threshold value 0x0fb [15:0] x r/w stage0_max_temp stage0 temporary maximum value 0x0fc [15:0] x r/w stage0_min_word0 stage0 minimum value fifo word0 0x0fd [15:0] x r/w stage0_min_word1 stage0 minimum value fifo word1 0x0fe [15:0] x r/w stage0_min_word2 stage0 minimum value fifo word2 0x0ff [15:0] x r/w stage0_min_word3 stage0 minimum value fifo word3 0x100 [15:0] x r/w stage0_min_avg stage0 average minimum fifo value 0x101 [15:0] x r/w stage0_low_thres hold stage0 low threshold value 0x102 [15:0] x r/w stage0_min_temp stage0 temporary minimum value 0x103 [15:0] x r/w unused se t unused register bits = 0
ad7142 rev. a | page 58 of 72 table 50. stage1 results registers address data bit default value type name description 0x104 [15:0] x r/w stage1_conv_data stage1 cdc 16-bit conversion data (copy of data in stage1_conv_data register) 0x105 [15:0] x r/w stage1_ff_word0 stage1 fast fifo word0 0x106 [15:0] x r/w stage1_ff_word1 stage1 fast fifo word1 0x107 [15:0] x r/w stage1_ff_word2 stage1 fast fifo word2 0x108 [15:0] x r/w stage1_ff_word3 stage1 fast fifo word3 0x109 [15:0] x r/w stage1_ff_word4 stage1 fast fifo word4 0x10a [15:0] x r/w stage1_ff_word5 stage1 fast fifo word5 0x10b [15:0] x r/w stage1_ff_word6 stage1 fast fifo word6 0x10c [15:0] x r/w stage1_ff_word7 stage1 fast fifo word7 0x10d [15:0] x r/w stage1_sf_word0 stage1 slow fifo word0 0x10e [15:0] x r/w stage1_sf_word1 stage1 slow fifo word1 0x10f [15:0] x r/w stage1_sf_word2 stage1 slow fifo word2 0x110 [15:0] x r/w stage1_sf_word3 stage1 slow fifo word3 0x111 [15:0] x r/w stage1_sf_word4 stage1 slow fifo word4 0x112 [15:0] x r/w stage1_sf_word5 stage1 slow fifo word5 0x113 [15:0] x r/w stage1_sf_word6 stage1 slow fifo word6 0x114 [15:0] x r/w stage1_sf_word7 stage1 slow fifo word7 0x115 [15:0] x r/w stage1_sf_ambient stage1 slow fifo ambient value 0x116 [15:0] x r/w stage1_ff_avg stage1 fast fifo average value 0x117 [15:0] x r/w stage1_cdc_word0 stage1 cdc fifo word0 0x118 [15:0] x r/w stage1_cdc_word1 stage1 cdc fifo word1 0x119 [15:0] x r/w stage1_max_word0 stage1 maximum value fifo word0 0x11a [15:0] x r/w stage1_max_word1 stage1 maximum value fifo word1 0x11b [15:0] x r/w stage1_max_word2 stage1 maximum value fifo word2 0x11c [15:0] x r/w stage1_max_word3 stage1 maximum value fifo word3 0x11d [15:0] x r/w stage1_max_avg stage1 average maximum fifo value 0x11e [15:0] x r/w stage1_high_threshold stage1 high threshold value 0x11f [15:0] x r/w stage1_max_temp stage1 temporary maximum value 0x120 [15:0] x r/w stage1_min_word0 stage1 minimum value fifo word0 0x121 [15:0] x r/w stage1_min_word1 stage1 minimum value fifo word1 0x122 [15:0] x r/w stage1_min_word2 stage1 minimum value fifo word2 0x123 [15:0] x r/w stage1_min_word3 stage1 minimum value fifo word3 0x124 [15:0] x r/w stage1_min_avg stage1 average minimum fifo value 0x125 [15:0] x r/w stage1_low_thres hold stage1 low threshold value 0x126 [15:0] x r/w stage1_min_temp stage1 temporary minimum value 0x127 [15:0] x r/w unused se t unused register bits = 0
ad7142 rev. a | page 59 of 72 table 51. stage2 results registers address data bit default value type name description 0x128 [15:0] x r/w stage2_conv_data stage2 cdc 16-bit conversion data (copy of data in stage2_conv_data register) 0x129 [15:0] x r/w stage2_ff_word0 stage2 fast fifo word0 0x12a [15:0] x r/w stage2_ff_word1 stage2 fast fifo word1 0x12b [15:0] x r/w stage2_ff_word2 stage2 fast fifo word2 0x12c [15:0] x r/w stage2_ff_word3 stage2 fast fifo word3 0x12d [15:0] x r/w stage2_ff_word4 stage2 fast fifo word4 0x12e [15:0] x r/w stage2_ff_word5 stage2 fast fifo word5 0x12f [15:0] x r/w stage2_ff_word6 stage2 fast fifo word6 0x130 [15:0] x r/w stage2_ff_word7 stage2 fast fifo word7 0x131 [15:0] x r/w stage2_sf_word0 stage2 slow fifo word0 0x132 [15:0] x r/w stage2_sf_word1 stage2 slow fifo word1 0x133 [15:0] x r/w stage2_sf_word2 stage2 slow fifo word2 0x134 [15:0] x r/w stage2_sf_word3 stage2 slow fifo word3 0x135 [15:0] x r/w stage2_sf_word4 stage2 slow fifo word4 0x136 [15:0] x r/w stage2_sf_word5 stage2 slow fifo word5 0x137 [15:0] x r/w stage2_sf_word6 stage2 slow fifo word6 0x138 [15:0] x r/w stage2_sf_word7 stage2 slow fifo word7 0x139 [15:0] x r/w stage2_sf_ambient stage2 slow fifo ambient value 0x13a [15:0] x r/w stage2_ff_avg stage2 fast fifo average value 0x13b [15:0] x r/w stage2_cdc_word0 stage2 cdc fifo word0 0x13c [15:0] x r/w stage2_cdc_word1 stage2 cdc fifo word1 0x13d [15:0] x r/w stage2_max_word0 stage2 maximum value fifo word0 0x13e [15:0] x r/w stage2_max_word1 stage2 maximum value fifo word1 0x13f [15:0] x r/w stage2_max_word2 stage2 maximum value fifo word2 0x140 [15:0] x r/w stage2_max_word3 stage2 maximum value fifo word3 0x141 [15:0] x r/w stage2_max_avg stage2 average maximum fifo value 0x142 [15:0] x r/w stage2_high_threshold stage2 high threshold value 0x143 [15:0] x r/w stage2_max_temp stage2 temporary maximum value 0x144 [15:0] x r/w stage2_min_word0 stage2 minimum value fifo word0 0x145 [15:0] x r/w stage2_min_word1 stage2 minimum value fifo word1 0x146 [15:0] x r/w stage2_min_word2 stage2 minimum value fifo word2 0x147 [15:0] x r/w stage2_min_word3 stage2 minimum value fifo word3 0x148 [15:0] x r/w stage2_min_avg stage2 average minimum fifo value 0x149 [15:0] x r/w stage2_low_thres hold stage2 low threshold value 0x14a [15:0] x r/w stage2_min_temp stage2 temporary minimum value 0x14b [15:0] x r/w unused set unused register bits = 0
ad7142 rev. a | page 60 of 72 table 52. stage3 results registers address data bit default value type name description 0x14c [15:0] x r/w stage3_conv_data stage3 cdc 16-bit conversion data (copy of data in stage3_conv_data register) 0x14d [15:0] x r/w stage3_ff_word0 stage3 fast fifo word0 0x14e [15:0] x r/w stage3_ff_word1 stage3 fast fifo word1 0x14f [15:0] x r/w stage3_ff_word2 stage3 fast fifo word2 0x150 [15:0] x r/w stage3_ff_word3 stage3 fast fifo word3 0x151 [15:0] x r/w stage3_ff_word4 stage3 fast fifo word4 0x152 [15:0] x r/w stage3_ff_word5 stage3 fast fifo word5 0x153 [15:0] x r/w stage3_ff_word6 stage3 fast fifo word6 0x154 [15:0] x r/w stage3_ff_word7 stage3 fast fifo word7 0x155 [15:0] x r/w stage3_sf_word0 stage3 slow fifo word0 0x156 [15:0] x r/w stage3_sf_word1 stage3 slow fifo word1 0x157 [15:0] x r/w stage3_sf_word2 stage3 slow fifo word2 0x158 [15:0] x r/w stage3_sf_word3 stage3 slow fifo word3 0x159 [15:0] x r/w stage3_sf_word4 stage3 slow fifo word4 0x15a [15:0] x r/w stage3_sf_word5 stage3 slow fifo word5 0x15b [15:0] x r/w stage3_sf_word6 stage3 slow fifo word6 0x15c [15:0] x r/w stage3_sf_word7 stage3 slow fifo word7 0x15d [15:0] x r/w stage3_sf_ambient stage3 slow fifo ambient value 0x15e [15:0] x r/w stage3_ff_avg stage3 fast fifo average value 0x15f [15:0] x r/w stage3_cdc_word0 stage3 cdc fifo word0 0x160 [15:0] x r/w stage3_cdc_word1 stage3 cdc fifo word1 0x161 [15:0] x r/w stage3_max_word0 stage3 maximum value fifo word0 0x162 [15:0] x r/w stage3_max_word1 stage3 maximum value fifo word1 0x163 [15:0] x r/w stage3_max_word2 stage3 maximum value fifo word2 0x164 [15:0] x r/w stage3_max_word3 stage3 maximum value fifo word3 0x165 [15:0] x r/w stage3_max_avg stage3 average maximum fifo value 0x166 [15:0] x r/w stage3_high_threshold stage3 high threshold value 0x167 [15:0] x r/w stage3_max_temp stage3 temporary maximum value 0x168 [15:0] x r/w stage3_min_word0 stage3 minimum value fifo word0 0x169 [15:0] x r/w stage3_min_word1 stage3 minimum value fifo word1 0x16a [15:0] x r/w stage3_min_word2 stage3 minimum value fifo word2 0x16b [15:0] x r/w stage3_min_word3 stage3 minimum value fifo word3 0x16c [15:0] x r/w stage3_min_avg stage3 average minimum fifo value 0x16d [15:0] x r/w stage3_low_thr eshold stage3 low threshold value 0x16e [15:0] x r/w stage3_min_temp stage3 temporary minimum value 0x16f [15:0] x r/w unused set unused register bits = 0
ad7142 rev. a | page 61 of 72 table 53. stage4 results registers address data bit default value type name description 0x170 [15:0] x r/w stage4_conv_data stage4 cdc 16-bit conversion data (copy of data in stage4_conv_data register) 0x171 [15:0] x r/w stage4_ff_word0 stage4 fast fifo word0 0x172 [15:0] x r/w stage4_ff_word1 stage4 fast fifo word1 0x173 [15:0] x r/w stage4_ff_word2 stage4 fast fifo word2 0x174 [15:0] x r/w stage4_ff_word3 stage4 fast fifo word3 0x175 [15:0] x r/w stage4_ff_word4 stage4 fast fifo word4 0x176 [15:0] x r/w stage4_ff_word5 stage4 fast fifo word5 0x177 [15:0] x r/w stage4_ff_word6 stage4 fast fifo word6 0x178 [15:0] x r/w stage4_ff_word7 stage4 fast fifo word7 0x179 [15:0] x r/w stage4_sf_word0 stage4 slow fifo word0 0x17a [15:0] x r/w stage4_sf_word1 stage4 slow fifo word1 0x17b [15:0] x r/w stage4_sf_word2 stage4 slow fifo word2 0x17c [15:0] x r/w stage4_sf_word3 stage4 slow fifo word3 0x17d [15:0] x r/w stage4_sf_word4 stage4 slow fifo word4 0x17e [15:0] x r/w stage4_sf_word5 stage4 slow fifo word5 0x17f [15:0] x r/w stage4_sf_word6 stage4 slow fifo word6 0x180 [15:0] x r/w stage4_sf_word7 stage4 slow fifo word7 0x181 [15:0] x r/w stage4_sf_ambient stage4 slow fifo ambient value 0x182 [15:0] x r/w stage4_ff_avg stage4 fast fifo average value 0x183 [15:0] x r/w stage4_cdc_word0 stage4 cdc fifo word0 0x184 [15:0] x r/w stage4_cdc_word1 stage4 cdc fifo word1 0x185 [15:0] x r/w stage4_max_word0 stage4 maximum value fifo word0 0x186 [15:0] x r/w stage4_max_word1 stage4 maximum value fifo word1 0x187 [15:0] x r/w stage4_max_word2 stage4 maximum value fifo word2 0x188 [15:0] x r/w stage4_max_word3 stage4 maximum value fifo word3 0x189 [15:0] x r/w stage4_max_avg stage4 average maximum fifo value 0x18a [15:0] x r/w stage4_high_threshold stage4 high threshold value 0x18b [15:0] x r/w stage4_max_temp stage4 temporary maximum value 0x18c [15:0] x r/w stage4_min_word0 stage4 minimum value fifo word0 0x18d [15:0] x r/w stage4_min_word1 stage4 minimum value fifo word1 0x18e [15:0] x r/w stage4_min_word2 stage4 minimum value fifo word2 0x18f [15:0] x r/w stage4_min_word3 stage4 minimum value fifo word3 0x190 [15:0] x r/w stage4_min_avg stage4 average minimum fifo value 0x191 [15:0] x r/w stage4_low_thres hold stage4 low threshold value 0x192 [15:0] x r/w stage4_min_temp stage4 temporary minimum value 0x193 [15:0] x r/w unused se t unused register bits = 0
ad7142 rev. a | page 62 of 72 table 54. stage5 results registers address data bit default value type name description 0x194 [15:0] x r/w stage5_conv_data stage5 cdc 16-bit conversion data (copy of data in stage5_conv_data register) 0x195 [15:0] x r/w stage5_ff_word0 stage5 fast fifo word0 0x196 [15:0] x r/w stage5_ff_word1 stage5 fast fifo word1 0x197 [15:0] x r/w stage5_ff_word2 stage5 fast fifo word2 0x198 [15:0] x r/w stage5_ff_word3 stage5 fast fifo word3 0x199 [15:0] x r/w stage5_ff_word4 stage5 fast fifo word4 0x19a [15:0] x r/w stage5_ff_word5 stage5 fast fifo word5 0x19b [15:0] x r/w stage5_ff_word6 stage5 fast fifo word6 0x19c [15:0] x r/w stage5_ff_word7 stage5 fast fifo word7 0x19d [15:0] x r/w stage5_sf_word0 stage5 slow fifo word0 0x19e [15:0] x r/w stage5_sf_word1 stage5 slow fifo word1 0x19f [15:0] x r/w stage5_sf_word2 stage5 slow fifo word2 0x1a0 [15:0] x r/w stage5_sf_word3 stage5 slow fifo word3 0x1a1 [15:0] x r/w stage5_sf_word4 stage5 slow fifo word4 0x1a2 [15:0] x r/w stage5_sf_word5 stage5 slow fifo word5 0x1a3 [15:0] x r/w stage5_sf_word6 stage5 slow fifo word6 0x1a4 [15:0] x r/w stage5_sf_word7 stage5 slow fifo word7 0x1a5 [15:0] x r/w stage5_sf_ambient stage5 slow fifo ambient value 0x1a6 [15:0] x r/w stage5_ff_avg stage5 fast fifo average value 0x1a7 [15:0] x r/w stage5_cdc_word0 stage5 cdc fifo word0 0x1a8 [15:0] x r/w stage5_cdc_word1 stage5 cdc fifo word1 0x1a9 [15:0] x r/w stage5_max_word0 stage5 maximum value fifo word0 0x1aa [15:0] x r/w stage5_max_word1 stage5 maximum value fifo word1 0x1ab [15:0] x r/w stage5_max_word2 stage5 maximum value fifo word2 0x1ac [15:0] x r/w stage5_max_word3 stage5 maximum value fifo word3 0x1ad [15:0] x r/w stage5_max_avg stage5 average maximum fifo value 0x1ae [15:0] x r/w stage5_high_thre shold stage5 high threshold value 0x1af [15:0] x r/w stage5_max_temp stage5 temporary maximum value 0x1b0 [15:0] x r/w stage5_min_word0 stage5 minimum value fifo word0 0x1b1 [15:0] x r/w stage5_min_word1 stage5 minimum value fifo word1 0x1b2 [15:0] x r/w stage5_min_word2 stage5 minimum value fifo word2 0x1b3 [15:0] x r/w stage5_min_word3 stage5 minimum value fifo word3 0x1b4 [15:0] x r/w stage5_min_avg stage5 average minimum fifo value 0x1b5 [15:0] x r/w stage5_low_thr eshold stage5 low threshold value 0x1b6 [15:0] x r/w stage5_min_temp stage5 temporary minimum value 0x1b7 [15:0] x r/w unused se t unused register bits = 0
ad7142 rev. a | page 63 of 72 table 55. stage6 results registers address data bit default value type name description 0x1b8 [15:0] x r/w stage6_conv_data stage6 cdc 16-bit conversion data (copy of data in stage6_conv_data register) 0x1b9 [15:0] x r/w stage6_ff_word0 stage6 fast fifo word0 0x1ba [15:0] x r/w stage6_ff_word1 stage6 fast fifo word1 0x1bb [15:0] x r/w stage6_ff_word2 stage6 fast fifo word2 0x1bc [15:0] x r/w stage6_ff_word3 stage6 fast fifo word3 0x1bd [15:0] x r/w stage6_ff_word4 stage6 fast fifo word4 0x1be [15:0] x r/w stage6_ff_word5 stage6 fast fifo word5 0x1bf [15:0] x r/w stage6_ff_word6 stage6 fast fifo word6 0x1c0 [15:0] x r/w stage6_ff_word7 stage6 fast fifo word7 0x1c1 [15:0] x r/w stage6_sf_word0 stage6 slow fifo word0 0x1c2 [15:0] x r/w stage6_sf_word1 stage6 slow fifo word1 0x1c3 [15:0] x r/w stage6_sf_word2 stage6 slow fifo word2 0x1c4 [15:0] x r/w stage6_sf_word3 stage6 slow fifo word3 0x1c5 [15:0] x r/w stage6_sf_word4 stage6 slow fifo word4 0x1c6 [15:0] x r/w stage6_sf_word5 stage6 slow fifo word5 0x1c7 [15:0] x r/w stage6_sf_word6 stage6 slow fifo word6 0x1c8 [15:0] x r/w stage6_sf_word7 stage6 slow fifo word7 0x1c9 [15:0] x r/w stage6_sf_ambient stage6 slow fifo ambient value 0x1ca [15:0] x r/w stage6_ff_avg stage6 fast fifo average value 0x1cb [15:0] x r/w stage6_cdc_word0 stage0 cdc fifo word0 0x1cc [15:0] x r/w stage6_cdc_word1 stage6 cdc fifo word1 0x1cd [15:0] x r/w stage6_max_word0 stage6 maximum value fifo word0 0x1ce [15:0] x r/w stage6_max_word1 stage6 maximum value fifo word1 0x1cf [15:0] x r/w stage6_max_word2 stage6 maximum value fifo word2 0x1d0 [15:0] x r/w stage6_max_word3 stage6 maximum value fifo word3 0x1d1 [15:0] x r/w stage6_max_avg stage6 average maximum fifo value 0x1d2 [15:0] x r/w stage6_high_threshold stage6 high threshold value 0x1d3 [15:0] x r/w stage6_max_temp stage6 temporary maximum value 0x1d4 [15:0] x r/w stage6_min_word0 stage6 minimum value fifo word0 0x1d5 [15:0] x r/w stage6_min_word1 stage6 minimum value fifo word1 0x1d6 [15:0] x r/w stage6_min_word2 stage6 minimum value fifo word2 0x1d7 [15:0] x r/w stage6_min_word3 stage6 minimum value fifo word3 0x1d8 [15:0] x r/w stage6_min_avg stage6 average minimum fifo value 0x1d9 [15:0] x r/w stage6_low_thr eshold stage6 low threshold value 0x1da [15:0] x r/w stage6_min_temp stage6 temporary minimum value 0x1db [15:0] x r/w unused set unused register bits = 0
ad7142 rev. a | page 64 of 72 table 56. stage7 results registers address data bit default value type name description 0x1dc [15:0] x r/w stage7_conv_data stage7 cdc 16-bit conversion data (copy of data in stage7_conv_data register) 0x1dd [15:0] x r/w stage7_ff_word0 stage7 fast fifo word0 0x1de [15:0] x r/w stage7_ff_word1 stage7 fast fifo word1 0x1df [15:0] x r/w stage7_ff_word2 stage7 fast fifo word2 0x1e0 [15:0] x r/w stage7_ff_word3 stage7 fast fifo word3 0x1e1 [15:0] x r/w stage7_ff_word4 stage7 fast fifo word4 0x1e2 [15:0] x r/w stage7_ff_word5 stage7 fast fifo word5 0x1e3 [15:0] x r/w stage7_ff_word6 stage7 fast fifo word6 0x1e4 [15:0] x r/w stage7_ff_word7 stage7 fast fifo word7 0x1e5 [15:0] x r/w stage7_sf_word0 stage7 slow fifo word0 0x1e6 [15:0] x r/w stage7_sf_word1 stage7 slow fifo word1 0x1e7 [15:0] x r/w stage7_sf_word2 stage7 slow fifo word2 0x1e8 [15:0] x r/w stage7_sf_word3 stage7 slow fifo word3 0x1e9 [15:0] x r/w stage7_sf_word4 stage7 slow fifo word4 0x1ea [15:0] x r/w stage7_sf_word5 stage7 slow fifo word5 0x1eb [15:0] x r/w stage7_sf_word6 stage7 slow fifo word6 0x1ec [15:0] x r/w stage7_sf_word7 stage7 slow fifo word7 0x1ed [15:0] x r/w stage7_sf_ambient stage7 slow fifo ambient value 0x1ee [15:0] x r/w stage7_ff_avg stage7 fast fifo average value 0x1ef [15:0] x r/w stage7_cdc_word0 stage7 cdc fifo word0 0x1f0 [15:0] x r/w stage7_cdc_word1 stage7 cdc fifo word1 0x1f1 [15:0] x r/w stage7_max_word0 stage7 maximum value fifo word0 0x1f2 [15:0] x r/w stage7_max_word1 stage7 maximum value fifo word1 0x1f3 [15:0] x r/w stage7_max_word2 stage7 maximum value fifo word2 0x1f4 [15:0] x r/w stage7_max_word3 stage7 maximum value fifo word3 0x1f5 [15:0] x r/w stage7_max_avg stage7 average maximum fifo value 0x1f6 [15:0] x r/w stage7_high_threshold stage7 high threshold value 0x1f7 [15:0] x r/w stage7_max_temp stage7 temporary maximum value 0x1f8 [15:0] x r/w stage7_min_word0 stage7 minimum value fifo word0 0x1f9 [15:0] x r/w stage7_min_word1 stage7 minimum value fifo word1 0x1fa [15:0] x r/w stage7_min_word2 stage7 minimum value fifo word2 0x1fb [15:0] x r/w stage7_min_word3 stage7 minimum value fifo word3 0x1fc [15:0] x r/w stage7_min_avg stage7 average minimum fifo value 0x1fd [15:0] x r/w stage7_low_thr eshold stage7 low threshold value 0x1fe [15:0] x r/w stage7_min_temp stage7 temporary minimum value 0x1ff [15:0] x r/w unused set unused register bits = 0
ad7142 rev. a | page 65 of 72 table 57. stage8 results registers address data bit default value type name description 0x200 [15:0] x r/w stage8_conv_data stage8 cdc 16-bit conversion data (copy of data in stage8_conv_data register) 0x201 [15:0] x r/w stage8_ff_word0 stage8 fast fifo word0 0x202 [15:0] x r/w stage8_ff_word1 stage8 fast fifo word1 0x203 [15:0] x r/w stage8_ff_word2 stage8 fast fifo word2 0x204 [15:0] x r/w stage8_ff_word3 stage8 fast fifo word3 0x205 [15:0] x r/w stage8_ff_word4 stage8 fast fifo word4 0x206 [15:0] x r/w stage8_ff_word5 stage8 fast fifo word5 0x207 [15:0] x r/w stage8_ff_word6 stage8 fast fifo word6 0x208 [15:0] x r/w stage8_ff_word7 stage8 fast fifo word7 0x209 [15:0] x r/w stage8_sf_word0 stage8 slow fifo word0 0x20a [15:0] x r/w stage8_sf_word1 stage8 slow fifo word1 0x20b [15:0] x r/w stage8_sf_word2 stage8 slow fifo word2 0x20c [15:0] x r/w stage8_sf_word3 stage8 slow fifo word3 0x20d [15:0] x r/w stage8_sf_word4 stage8 slow fifo word4 0x20e [15:0] x r/w stage8_sf_word5 stage8 slow fifo word5 0x20f [15:0] x r/w stage8_sf_word6 stage8 slow fifo word6 0x210 [15:0] x r/w stage8_sf_word7 stage8 slow fifo word7 0x211 [15:0] x r/w stage8_sf_ambient stage8 slow fifo ambient value 0x212 [15:0] x r/w stage8_ff_avg stage8 fast fifo average value 0x213 [15:0] x r/w stage8_cdc_word0 stage8 cdc fifo word0 0x214 [15:0] x r/w stage8_cdc_word1 stage8 cdc fifo word1 0x215 [15:0] x r/w stage8_max_word0 stage8 maximum value fifo word0 0x216 [15:0] x r/w stage8_max_word1 stage8 maximum value fifo word1 0x217 [15:0] x r/w stage8_max_word2 stage8 maximum value fifo word2 0x218 [15:0] x r/w stage8_max_word3 stage8 maximum value fifo word3 0x219 [15:0] x r/w stage8_max_avg stage8 average maximum fifo value 0x21a [15:0] x r/w stage8_high_threshold stage8 high threshold value 0x21b [15:0] x r/w stage8_max_temp stage8 temporary maximum value 0x21c [15:0] x r/w stage8_min_word0 stage8 minimum value fifo word0 0x21d [15:0] x r/w stage8_min_word1 stage8 minimum value fifo word1 0x21e [15:0] x r/w stage8_min_word2 stage8 minimum value fifo word2 0x21f [15:0] x r/w stage8_min_word3 stage8 minimum value fifo word3 0x220 [15:0] x r/w stage8_min_avg stage8 average minimum fifo value 0x221 [15:0] x r/w stage8_low_thres hold stage8 low threshold value 0x222 [15:0] x r/w stage8_min_temp stage7 temporary minimum value 0x223 [15:0] x r/w unused se t unused register bits = 0
ad7142 rev. a | page 66 of 72 table 58. stage9 results registers address data bit default value type name description 0x224 [15:0] x r/w stage9_conv_data stage9 cdc 16-bit conversion data (copy of data in stage9_conv_data register) 0x225 [15:0] x r/w stage9_ff_word0 stage9 fast fifo word0 0x226 [15:0] x r/w stage9_ff_word1 stage9 fast fifo word1 0x227 [15:0] x r/w stage9_ff_word2 stage9 fast fifo word2 0x228 [15:0] x r/w stage9_ff_word3 stage9 fast fifo word3 0x229 [15:0] x r/w stage9_ff_word4 stage9 fast fifo word4 0x22a [15:0] x r/w stage9_ff_word5 stage9 fast fifo word5 0x22b [15:0] x r/w stage9_ff_word6 stage9 fast fifo word6 0x22c [15:0] x r/w stage9_ff_word7 stage9 fast fifo word7 0x22d [15:0] x r/w stage9_sf_word0 stage9 slow fifo word0 0x22e [15:0] x r/w stage9_sf_word1 stage9 slow fifo word1 0x22f [15:0] x r/w stage9_sf_word2 stage9 slow fifo word2 0x230 [15:0] x r/w stage9_sf_word3 stage9 slow fifo word3 0x231 [15:0] x r/w stage9_sf_word4 stage9 slow fifo word4 0x232 [15:0] x r/w stage9_sf_word5 stage9 slow fifo word5 0x233 [15:0] x r/w stage9_sf_word6 stage9 slow fifo word6 0x234 [15:0] x r/w stage9_sf_word7 stage9 slow fifo word7 0x235 [15:0] x r/w stage9_sf_ambient stage9 slow fifo ambient value 0x236 [15:0] x r/w stage9_ff_avg stage9 fast fifo average value 0x237 [15:0] x r/w stage9_cdc_word0 stage9 cdc fifo word0 0x238 [15:0] x r/w stage9_cdc_word1 stage9 cdc fifo word1 0x239 [15:0] x r/w stage9_max_word0 stage9 maximum value fifo word0 0x23a [15:0] x r/w stage9_max_word1 stage9 maximum value fifo word1 0x23b [15:0] x r/w stage9_max_word2 stage9 maximum value fifo word2 0x23c [15:0] x r/w stage9_max_word3 stage9 maximum value fifo word3 0x23d [15:0] x r/w stage9_max_avg stage9 average maximum fifo value 0x23e [15:0] x r/w stage9_high_threshold stage9 high threshold value 0x23f [15:0] x r/w stage9_max_temp stage9 temporary maximum value 0x240 [15:0] x r/w stage9_min_word0 stage9 minimum value fifo word0 0x241 [15:0] x r/w stage9_min_word1 stage9 minimum value fifo word1 0x242 [15:0] x r/w stage9_min_word2 stage9 minimum value fifo word2 0x243 [15:0] x r/w stage9_min_word3 stage9 minimum value fifo word3 0x244 [15:0] x r/w stage9_min_avg stage9 average minimum fifo value 0x245 [15:0] x r/w stage9_low_thres hold stage9 low threshold value 0x246 [15:0] x r/w stage9_min_temp stage9 temporary minimum value 0x247 [15:0] x r/w unused se t unused register bits = 0
ad7142 rev. a | page 67 of 72 table 59. stage10 results registers address data bit default value type name description 0x248 [15:0] x r/w stage10_conv_data stage10 cdc 16-bit conversion data (copy of data in stage10_conv_data register) 0x249 [15:0] x r/w stage10_ff_word0 stage10 fast fifo word0 0x24a [15:0] x r/w stage10_ff_word1 stage10 fast fifo word1 0x24b [15:0] x r/w stage10_ff_word2 stage10 fast fifo word2 0x24c [15:0] x r/w stage10_ff_word3 stage10 fast fifo word3 0x24d [15:0] x r/w stage10_ff_word4 stage10 fast fifo word4 0x24e [15:0] x r/w stage10_ff_word5 stage10 fast fifo word5 0x24f [15:0] x r/w stage10_ff_word6 stage10 fast fifo word6 0x250 [15:0] x r/w stage10_ff_word7 stage10 fast fifo word7 0x251 [15:0] x r/w stage10_sf_word0 stage10 slow fifo word0 0x252 [15:0] x r/w stage10_sf_word1 stage10 slow fifo word1 0x253 [15:0] x r/w stage10_sf_word2 stage10 slow fifo word2 0x254 [15:0] x r/w stage10_sf_word3 stage10 slow fifo word3 0x255 [15:0] x r/w stage10_sf_word4 stage10 slow fifo word4 0x256 [15:0] x r/w stage10_sf_word5 stage10 slow fifo word5 0x257 [15:0] x r/w stage10_sf_word6 stage10 slow fifo word6 0x258 [15:0] x r/w stage10_sf_word7 stage10 slow fifo word7 0x259 [15:0] x r/w stage10_sf_ambient stage10 slow fifo ambient value 0x25a [15:0] x r/w stage10_ff_avg stage10 fast fifo average value 0x25b [15:0] x r/w stage10_cdc_word0 stage10 cdc fifo word0 0x25c [15:0] x r/w stage10_cdc_word1 stage10 cdc fifo word1 0x25d [15:0] x r/w stage10_max_word0 stage10 maximum value fifo word0 0x25e [15:0] x r/w stage10_max_word1 stage10 maximum value fifo word1 0x25f [15:0] x r/w stage10_max_word 2 stage10 maximum value fifo word2 0x260 [15:0] x r/w stage10_max_word3 stage10 maximum value fifo word3 0x261 [15:0] x r/w stage10_max_avg stage10 average maximum fifo value 0x262 [15:0] x r/w stage10_high_thres hold stage10 high threshold value 0x263 [15:0] x r/w stage10_max_temp stage10 temporary maximum value 0x264 [15:0] x r/w stage10_min_word0 stage10 minimum value fifo word0 0x265 [15:0] x r/w stage10_min_word1 stage10 minimum value fifo word1 0x266 [15:0] x r/w stage10_min_word2 stage10 minimum value fifo word2 0x267 [15:0] x r/w stage10_min_word3 stage10 minimum value fifo word3 0x268 [15:0] x r/w stage10_min_avg stage10 average minimum fifo value 0x269 [15:0] x r/w stage10_low_threshold stage10 low threshold value 0x26a [15:0] x r/w stage10_min_temp stage10 temporary minimum value 0x26b [15:0] x r/w unused set unused register bits = 0
ad7142 rev. a | page 68 of 72 table 60. stage11 results registers address data bit default value type name description 0x26c [15:0] x r/w stage11_conv_data stage11 cdc 16-bit conversion data (copy of data in stage11_conv_data register) 0x26d [15:0] x r/w stage11_ff_word0 stage11 fast fifo word0 0x26e [15:0] x r/w stage11_ff_word1 stage11 fast fifo word1 0x26f [15:0] x r/w stage11_ff_word2 stage11 fast fifo word2 0x270 [15:0] x r/w stage11_ff_word3 stage11 fast fifo word3 0x271 [15:0] x r/w stage11_ff_word4 stage11 fast fifo word4 0x272 [15:0] x r/w stage11_ff_word5 stage11 fast fifo word5 0x273 [15:0] x r/w stage11_ff_word6 stage11 fast fifo word6 0x274 [15:0] x r/w stage11_ff_word7 stage11 fast fifo word7 0x275 [15:0] x r/w stage11_sf_word0 stage11 slow fifo word0 0x276 [15:0] x r/w stage11_sf_word1 stage11 slow fifo word1 0x277 [15:0] x r/w stage11_sf_word2 stage11 slow fifo word2 0x278 [15:0] x r/w stage11_sf_word3 stage11 slow fifo word3 0x279 [15:0] x r/w stage11_sf_word4 stage11 slow fifo word4 0x27a [15:0] x r/w stage11_sf_word5 stage11 slow fifo word5 0x27b [15:0] x r/w stage11_sf_word6 stage11 slow fifo word6 0x27c [15:0] x r/w stage11_sf_word7 stage11 slow fifo word7 0x27d [15:0] x r/w stage11_sf_ambient stage11 slow fifo ambient value 0x27e [15:0] x r/w stage11_ff_avg stage11 fast fifo average value 0x27f [15:0] x r/w stage11_cdc_word0 stage11 cdc fifo word0 0x280 [15:0] x r/w stage11_cdc_word1 stage11 cdc fifo word1 0x281 [15:0] x r/w stage11_max_word0 stage11 maximum value fifo word0 0x282 [15:0] x r/w stage11_max_word1 stage11 maximum value fifo word1 0x283 [15:0] x r/w stage11_max_word2 stage11 maximum value fifo word2 0x284 [15:0] x r/w stage11_max_word3 stage11 maximum value fifo word3 0x285 [15:0] x r/w stage11_max_avg stage11 average maximum fifo value 0x286 [15:0] x r/w stage11_high_thres hold stage11 high threshold value 0x287 [15:0] x r/w stage11_max_temp stage11 temporary maximum value 0x288 [15:0] x r/w stage11_min_word0 stage11 minimum value fifo word0 0x289 [15:0] x r/w stage11_min_word1 stage11 minimum value fifo word1 0x28a [15:0] x r/w stage11_min_word2 stage11 minimum value fifo word2 0x28b [15:0] x r/w stage11_min_word3 stage11 minimum value fifo word3 0x28c [15:0] x r/w stage11_min_avg stage11 average minimum fifo value 0x28d [15:0] x r/w stage11_low_threshold stage11 low threshold value 0x28e [15:0] x r/w stage11_min_temp stage11 temporary minimum value 0x28f [15:0] x r/w unused set unused register bits = 0
ad7142 rev. a | page 69 of 72 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 60. 32-lead frame chip scale package [lfcsp_vq] 5 mm 5 mm very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model temperature range serial interface desc ription package description package option ad7142acpz-reel 1 C40c to +85c spi interface 32-lead lfcsp_vq cp-32-2 ad7142acpz-500rl7 1 C40c to +85c spi interface 32-lead lfcsp_vq cp-32-2 ad7142acpz-1reel 1 C40c to +85c i 2 c interface 32-lead lfcsp_vq cp-32-2 AD7142ACPZ-1500RL7 1 C40c to +85c i 2 c interface 32-lead lfcsp_vq cp-32-2 eval-ad7142ebz 1 spi interface evaluation board eval-ad7142-1ebz 1 i 2 c interface evaluation board 1 z = pb-free part.
ad7142 rev. a | page 70 of 72 notes
ad7142 rev. a | page 71 of 72 notes
ad7142 rev. a | page 72 of 72 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05702-0-1/07(a)

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